AD9528 datasheet(64/68 Pages) AD

64 / 68 page

Data Sheet

AD9528

Rev. C | Page 63 of 67

POWER-DOWN CONTROL (REGISTER 0x0500 TO REGISTER 0x0504)

Table 64. Power-Down Control Enable

Address

Bits

Bit Name

Description

0x0500

[7:5]

Reserved

Bias generation power-down

disable or power-down

0 = power-down

1 = normal operation

PLL2 power-down enable

0 = normal operation

1 = power-down

PLL1 power-down enable

0 = normal operation

1 = power-down

Clock distribution power-down

enable

0 = normal operation

1 = power-down

Chip power-down enable

0 = normal operation

1 = power-down

Table 65. Output Channel Power-Down Control

Address

Bits

Bit Name

Description

0x0501

Channel 7 power-down

0 = normal operation

1 = Channel 7 power-down

Channel 6 power-down

0 = normal operation

1 = Channel 6 power-down

Channel 5 power-down

0 = normal operation

1 = Channel 5 power-down

Channel 4 power-down

0 = normal operation

1 = Channel 4 power-down

Channel 3 power-down

0 = normal operation

1 = Channel 3 power-down

Channel 2 power-down

0 = normal operation

1 = Channel 2 power-down

Channel 1 power-down

0 = normal operation

1 = Channel 1 power-down

Channel 0 power-down

0 = normal operation

1 = Channel 0 power-down

0x0502

[7:6]

Reserved

Channel 13 power-down

0 = normal operation

1 = Channel 13 power-down

Channel 12 power-down

0 = normal operation

1 = Channel 12 power-down

Channel 11 power-down

0 = normal operation

1 = Channel 11 power-down

Channel 10 power-down

0 = normal operation

1 = Channel 10 power-down

Channel 9 power-down

0 = normal operation

1 = Channel 9 power-down

Channel 8 power-down

0 = normal operation

1 = Channel 8 power-down

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