AD9528 datasheet(31/68 Pages) AD

31 / 68 page

AD9528

Data Sheet

Rev. C | Page 30 of 67

Figure 32. Clock Distribution Paths for PLL1, PLL2, and SYSREF

Frequency Sources

The following are various channel limitations, depending on the

channel configuration:

•

Analog fine delay is supported for all channels, regardless

of the input frequency source selected.

•

Digital coarse delay is only supported when the channel

divider is used. When SYSREF is used as the frequency

source, the signal must be retimed by the output of the

channel divider to use the digital coarse delay.

•

Output channel synchronization is performed by

synchronously resetting the 8-bit channel divider via the

sync outputs bit in Register 0x032A, Bit 0. Therefore, the

8-bit divider path must be used to support synchronization. If

SYSREF is the frequency source to an output, the SYSREF

signal must be resampled by the output of the channel

divider for a SYNC to occur.

Clock Dividers

The output clock distribution dividers are referred to as D0 to

D13, corresponding to output channels OUT0 through OUT13,

respectively. Each divider is programmable with 8 bits of

precision equal to any number from 1 through 256. Dividers

have duty cycle correction set to provide nominal 50% duty

cycle, even for odd divides. Note that a sync output command

must be issued after changing the divide value to ensure the

intended divide ratio occurs at the channel output(s).

Digital Coarse Delay

The AD9528 supports programmable phase offsets from 0 to 63

steps (6 bits) in half period increments of the RF VCO divider

output frequency. Note that a sync output command must be

issued after the new phase offset(s) are programmed to ensure

the intended phase offset occurs at the channel output(s). This

is accomplished by programming the new phase offset and then

issuing a sync command via Register 0x032A, Bit 0. All outputs

are disabled temporarily while the sync is active, unless the

channel is programmed to ignore the sync command. The ignore

sync command for each channel is controlled via Register 0x032B

and Register 0x032C.

Analog Fine Delay

Each channel includes a 4-bit fine analog delay block intended

to provide substantially smaller delay steps compared to the half

cycle of the RF VCO divider output. The fine analog delay enable

bit in each channel activates the fine delay path; when the enable

bit is asserted with the four delay bits = 0000, the minimum

insertion delay is nominally 425 ps. Full-scale delay = 1111 adds

another 496 ps of additional delay. The average fine delay

resolution step is approximately 31 ps.

Output Channel Power-Down

Each output channel has independent power-down control via

reduced with each channel powered down, keeping the output

static until the user is ready to disable the channel power-down

control. In addition, Register 0x0503 and Register 0x0504 offer

additional power savings via LDO power-down control for each

channel output.

Output Drivers

Each channel and corresponding output driver has a dedicated

internal LDO to power both the channel and output driver. The

equivalent output driver circuits are shown in Figure 33 and

Figure 34. The output driver design supports a common

external 100 Ω differential resistor for both HSTL and LVDS

driver modes. In LVDS mode, a current of 3.5 mA causes a

350 mV peak voltage across the 100 Ω load resistor. In LVDS

boost mode, a current of 4.5 mA causes a 450 mV peak voltage

across the 100 Ω load resistor. Similarly, in HSTL mode, a

current of 9 mA causes a 900 mV peak voltage across the 100 Ω

load resistor.

Figure 33. LVDS Output Driver

Figure 34. HSTL Output Driver

CLOCK DISTRIBUTION

PLL1

PLL2

SYSREF

8-BIT DIVIDER

WITH

COARSE DELAY

SYNC

OUTx

FINE

DELAY

VREG = 1.8V

LVDS

COMMON MODE

CIRCUIT

1.25V LVDS

3.5mA/4.5mA

100Ω

LOAD

–

OUT

VREG = 1.8V

50Ω

100Ω

LOAD

–

OUT

50Ω

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