Data Sheet

ADF4355

Rev. A | Page 27 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7

DB6

DB5 DB4

DB3

DB2

DB1

DB0

1

00

0

0

RESERVED

CONTROL

BITS

0

1

011

0

1

0

0

0

1

0

0

0

10

C3(0) C2(0) C1(0)

C4(1)

0

0

0

0

0

0

0

Figure 38. Register 8 (0x102D0428)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

VC5

VC4

VC3

VC2

VC1

TIMEOUT

CONTROL

BITS

TL10

TL9

TL8

TL7

TL6

TL5

TL4

TL3

TL2

TL1

AL5

AL4

AL3

AL2

AL1

SL5

SL4

SL3

SL2

SL1

C3(0) C2(0) C1(1)

C4(1)

VC6

VC7

VC8

TL10

TL9

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

TL2

TL1

TIMEOUT

00

0

1

1

00

1

0

2

..

.

.

.

..

.

.

.

..

.

.

.

1

1

0

0

1020

1

1

0

1

1021

1

1

1

0

1022

1

1

1

1

1023

AL5

AL4

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

AL2

AL1

ALC WAIT

00

0

1

1

00

1

0

2

..

.

.

.

..

.

.

.

..

.

.

.

11

0

0

28

11

0

1

29

11

1

0

30

11

1

1

31

VC8

VC7

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

VC2

VC1

VCO BAND DIV

00

0

1

1

00

1

0

2

..

.

.

.

..

.

.

.

..

.

.

.

11

0

0

252

11

0

1

253

11

1

0

254

11

1

1

255

VCO BAND DIVISION

SL5

SL4

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

SL2

SL1

SLC WAIT

00

0

1

1

00

1

0

2

..

.

.

.

..

.

.

.

..

.

.

.

11

0

0

28

11

0

1

29

11

1

0

30

11

1

1

31

SYNTHESIZER

LOCK TIMEOUT

AUTOMATIC LEVEL TIMEOUT

Figure 39. Register 9

REGISTER 8

The bits in this register are reserved and must be programmed

as described in Figure 38, using a hexadecimal word of

0x102D0428.

REGISTER 9

Control Bits

With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 39

shows the input data format for programming this register.

VCO Band Division

VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band

division clock. Determine the value of this clock by PFD/(band

division × 16) such that the result is <150 kHz.

Timeout

TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the

VCO band select. Use this value as a variable in the other VCO

calibration settings.

Automatic Level Calibration Timeout

AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the

automatic level calibration of the VCO. This function combines

the PFD frequency, the timeout variable, and ALC wait variable.

Choose ALC such that the following equation is always greater

than 50 μs.

(Timeout × ALC Wait/PFD Frequency) > 50 μs

Synthesizer Lock Timeout

SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout

the following equation:

(Timeout × Synthesizer Lock Timeout/PFD Frequency) > 20 μs