Data Sheet

ADF4355

Rev. A | Page 21 of 35

P24

P23

..........

P2

P1

PHASE VALUE (PHASE)

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

16777212

1

1

..........

0

1

16777213

1

1

..........

1

0

16777214

1

1

.........

1

1

16777215

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

PA1P24

P23P22

P21

24-BIT PHASE VALUE (PHASE)

CONTROL

BITS

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

C3(0) C2(1) C1(1)

C4(0)

PR1

SD1

0

PA1

PHASE

ADJUST

0

DISABLED

1

ENABLED

PR1

PHASE

RESYNC

0DISABLED

1

ENABLED

SD1

SD LOAD

RESET

0ON REGISTER0 UPDATE

1DISABLED

Figure 33. Register 3

REGISTER 3

Control Bits

With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 33

shows the input data format for programming this register.

Reserved

Bit DB31 is reserved and must be set to 0.

SD Load Reset

When writing to Register 0, the Σ-Δ modulator resets. For

applications when the phase is continually adjusted, this may

not be desirable; therefore, in these cases, the Σ-Δ reset can be

disabled by writing a 1 to the SD1 bit (Bit DB30).

Phase Resync

To use the phase resynchronization feature, the PR1 bit (Bit DB29)

must be set to 1. If unused, the bit can be programmed to 0. The

phase resync timer must also be used in Register 12 to ensure that

the resynchronization feature is applied after the PLL has settled

to the final frequency. If the PLL has not settled to the final frequency,

phase resync may not function correctly. Resynchronization is

useful in phased array and beam forming applications. It ensures

repeatability of output phase when programming the same

frequency. In phase critical applications that use frequencies

requiring the output divider (<3400 MHz), it is necessary to

feed the N divider with the divided VCO frequency rather than

from the fundamental VCO frequency.

This is achieved by programming the D13 bit (Bit DB24) in

Register 6 to 0, which ensures divided feedback to the N divider.

Phase resynchronization only operateswhen FRAC2 = 0.

For resync applications, enable the SD load reset in Register 3

by setting DB30 to 0.

Phase Adjust

To adjust the relative output phase of the ADF4355 on each

Register 0 update, set the PA1 bit (Bit DB28) to 1. This feature

differs from the resynchronization feature in that it is useful

when adjustments to the phase are made continually in an

application. For this function, disable the VCO automatic

calibration by setting the AC1 bit (Bit DB21) in Register 0 to 1

and disable the SD load reset by setting the SD1 bit (Bit DB30)

in Register 3 to 1. Note that phase resync and phase adjust

cannot be used simultaneously.

24-Bit Phase Value

The phase of the RF output frequency can adjust in 24-bit steps;

phase is set by

(Phase Value/16,777,216) × 360°

When the phase value is programmed to Register 3, each

subsequent adjustment of Register 0 increments the phase by

the value in this equation.