Data Sheet

ADF4355

Rev. A | Page 23 of 35

Reference Mode

The ADF4355 permits use of either differential or single-ended

reference sources.

For optimum integer boundary spur performance, use the

single-ended setting for all references up to 250 MHz (even if

using a differential reference signal). Use the differential setting for

reference frequencies above 250 MHz.

Level Select

To assist with logic compatibility, MUXOUT is programmable to

two logic levels. Set the U5 bit (Bit DB8) to 0 to select 1.8 V logic,

and set it to 1 to select 3.3 V logic.

Phase Detector (PD) Polarity

The U4 bit (Bit DB7) sets the phase detector polarity. When a

passive loop filter or a noninverting active loop filter is used,

set DB7 to 1 (positive). If an active filter with an inverting

characteristic is used, set this bit to 0 (negative).

Power-Down

The U3 bit (Bit DB6) sets the programmable power-down mode.

Setting DB6 to 1 performs a power-down. Setting DB6 to 0

returns the synthesizer to normal operation. In software power-

down mode, the ADF4355 retains all information in its registers.

The register contents are only lost if the supply voltages are

removed.

When power-down activates, the following events occur:

•

The synthesizer counters are forced to their load state

conditions.

•

The VCO powers down.

•

The charge pump is forced into three-state mode.

•

The digital lock detect circuitry resets.

•

stages are disabled.

•

The input registers remain active and capable of loading

and latching data.

Charge Pump Three-State

Setting the U2 bit (Bit DB5) to 1 puts the charge pump into

three-state mode. Set DB5 to 0 for normal operation.

Counter Reset

The U1 bit (Bit DB4) resets the R counter, N counter, and

VCO band select of the ADF4355. When DB4 is set to 1, the RF

synthesizer N counter and R counter, and the VCO band select,

are reset. For normal operation, set DB4 to 0. Toggling counter

reset (Bit DB4) is also required when changing frequency (see

the Frequency Update Sequence section for additional details).

REGISTER 5

The bits in Register 5 are reserved and must be programmed as

described in Figure 35, using a hexadecimal word of 0x00800025.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

0

0

0

0

0

0

0

0

C4(0) C3(1) C2(0)

CONTROL

BITS

0

0

RESERVED

DB0

C1(1)

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

Figure 35. Register 5 (0x00800025)