ADF4355BCPZ datasheet(4/36 Pages) AD

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Data Sheet

ADF4355

Rev. A | Page 3 of 35

SPECIFICATIONS

AVDD = DVDD = VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ,

dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

REFINA/REFINB CHARACTERISTICS

Input Frequency

For f < 10 MHz, ensure slew rate > 21V/µs

Single-Ended Mode

250

MHz

Differential Mode

600

MHz

Doubler Enabled

100

MHz

Doubler is set in Register 4, Bit DB26

Input Sensitivity

Single-Ended Mode

0.4

AVDD

V p-p

REFINA biased at AVDD/2; ac coupling

ensures AVDD/2 bias

Differential Mode

0.4

1.8

V p-p

LVDS and LVPECL compatible,

REFINA/REFINB biased at 2.1 V;

ac coupling ensures 2.1 V bias

Input Capacitance

Single-Ended Mode

6.9

Differential Mode

1.4

Input Current

±60

µA

Single-ended reference programmed

±250

µA

Differential reference programmed

Phase Detector Frequency

125

MHz

CHARGE PUMP (CP)

Charge Pump Current, Sink/Source

ICP

RSET = 5.1 kΩ

High Value

4.8

Low Value

0.3

RSET Range

5.1

kΩ

Fixed

Current Matching

0.5 V ≤ VCP1 ≤ VP − 0.5 V

ICP vs. VCP1

0.5 V ≤ VCP1 ≤ VP − 0.5 V

ICP vs. Temperature

1.5

VCP1 = 2.5 V

LOGIC INPUTS

Input High Voltage

VINH

1.5

Input Low Voltage

VINL

0.6

Input Current

IINH/IINL

±1

µA

Input Capacitance

CIN

3.0

LOGIC OUTPUTS

Output High Voltage

VOH

DVDD − 0.4

1.5

1.8

1.8 V output selected

Output High Current

IOH

500

µA

Output Low Voltage

VOL

0.4

IOL2 = 500 µA

POWER SUPPLIES

Analog Power

AVDD

3.15

3.45

Digital Power and RF Supply Voltage

DVDD, VRF

AVDD

Voltages must equal AVDD

Charge Pump and VCO Voltage

VP, VVCO

4.75

5.0

5.25

VP must equal VVCO

Charge Pump Supply Power Current

Digital Power Supply Current +

Analog Power Supply Curent3

DIDD, AIDD

Output Dividers

6 to 36

Each output divide by 2 consumes 6 mA

Supply Current

IVCO

RFOUTA±/RFOUTB± Supply Current

OUT

16/20/

42/55

20/35/

50/70

RF output stage is programmable;

RFOUTB+/RFOUTB− powered off

Low Power Sleep Mode

500

µA

Hardware power-down

1000

µA

Software power-down

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