ADF4355

Data Sheet

Rev. A | Page 24 of 35

D3

RF OUT

0DISABLED

1

ENABLED

D2

D1

OUTPUT POWER

0

0

–4dBm

0

1

–1dBm

10+2dBm

11+5dBm

D5

D4

AUXILIARY OUTPUT POWER

0

0

–4dBm

0

1

–1dBm

10

+2dBm

11

+5dBm

D6

AUXILIARY OUT

0DISABLED

1

ENABLED

D8

MUTE TILL

LOCK DETECT

0

MUTE DISABLED

1

MUTE ENABLED

D13

FEEDBACK

SELECT

0

FUNDAMEN TAL

1

DIVIDED

D12

D11

RF DIVIDER SELECT

00

÷1

00

÷2

01

÷4

01

÷8

D10

0

1

0

1

1

1

1

0

0

1

÷16

÷32

÷64

0

1

0

BL8

BL7

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

BL2

BL1

BLEED CURRENT

0

0

0

1

1

(3.75µA)

0

0

1

0

2

(7.5µA)

..

.

.

.

..

.

.

.

..

.

.

.

1

1

0

0

252

(945µA)

1

1

0

1

253

(948.75µA)

1

1

1

0

254

(952.5µA)

1

1

1

1

255

(956.25µA)

BL9

BLEED CURRENT

0

ENABLED

1

DISABLED

BL10 GATED BLEED

0

ENABLED

1

DISABLED

RF DIVIDER

RF

OUTPUT

POWER

DB31

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

D13

D12

D11

D10

BL1

0

D8

0

D6

D5

D4

D3

D2

D1

C4(0) C3(1) C2(1)

CONTROL

BITS

CHARGE PUMP BLEED CURRENT

AUX RF

OUTPUT

POWER

RESERVED

C1(0)

BL2

BL3

BL4

BL5

BL6

BL7

BL8

BL9

BL10

Figure 36. Register 6

REGISTER 6

Control Bits

With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 36

shows the input data format for programming this register.

Reserved

Bit DB31 is reserved and must be set to 0.

Gated Bleed

Bleed currents can improve phase noise and spurs; however, due

to a potential impact on lock time, the gated bleed bit, BL10

(Bit DB30), if set to 1, ensures bleed currents are not switched

on until the digital lock detect asserts logic high. Note that this

function requires digital lock detect to be enabled.

Negative Bleed

Use of constant negative bleed is recommended for most

applications because it improves the linearity of the charge

pump leading to lower noise and spurs than leaving negative

bleed off. To enable negative bleed, write 1 to BL9 (Bit DB29),

and to disable negative bleed, write 0 to BL9 (Bit DB29).

Use negative bleed only when operating in fractional-N mode,

that is, FRAC1 or FRAC2 is not equal to 0. Do not use negative

Reserved

Bits[DB28:DB25] are reserved and must be set to 1010.

Feedback Select

D13 (Bit DB24) selects the feedback from the output of the

VCO to the N counter. When D13 is set to 1, the signal is taken

directly from the VCO. When this bit is set to 0, the signal is

taken from the output of the output dividers. The dividers

enable coverage of the wide frequency band (54 MHz to

6800 MHz). When the divider is enabled and the feedback

signal is taken from the output, the RF output signals of two

separately configured PLLs are in phase. Divided feedback is

useful in some applications where the positive interference of

signals is required to increase the power.

RF Divider Select

D12 to D10 (Bits[DB23:DB21]) select the value of the RF output

divider (see Figure 36).