ADF4355BCPZ datasheet(32/36 Pages) AD

32 / 36 page

Data Sheet

ADF4355

Rev. A | Page 31 of 35

OPTIMIZING JITTER

For lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of in-band noise from

the PLL. Set the PLL filter bandwidth such that the in-band noise

of the PLL intersects with the open-loop noise of the VCO,

minimizing the contribution of both to the overall noise.

Use the ADIsimPLL™ design tool for this task.

SPUR MECHANISMS

This section describes the two different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4355.

Integer Boundary Spurs

One mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (the purpose of a

fractional-N synthesizer), spur sidebands appear on the VCO

output spectrum at an offset frequency that corresponds to the

beat note or the difference in frequency between an integer

multiple of the reference and the VCO frequency. These spurs

are attenuated by the loop filter and are more noticeable on

channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth (thus

the name, integer boundary spurs).

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop may cause a problem. Feedthrough of

low levels of on-chip reference switching noise, through the

prescaler back to the VCO, can result in reference spur levels

as high as −80 dBc.

LOCK TIME

The PLL lock time divides into a number of settings. All of

these are modeled in the ADIsimPLL design tool. Faster lock

times than those detailed in this data sheet are possible; contact

your local Analog Devices, Inc., sales representative for more

information.

Lock Time—A Worked Example

Assuming fPFD = 61.44 MHz,

VCO Band Div = Ceiling(fPFD/2,400,000) = 26

where Ceiling() rounds up to the nearest integer.

By combining the following two equations:

ALC Wait > (50 µs × fPFD)/Timeout

Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout

The following is found:

ALC Wait = 2.5 × Synthesizer Lock Timeout

Maximize ALC Wait (to reduce Timeout to minimize time) so

that ALC Wait = 30 and Synthesizer Lock Timeout = 12.

Finally, ALC Wait > (50 µs × fPFD)/Timeout, is rearranged as

Timeout = Ceiling((fPFD × 50 µs)/ALC Wait)

Timeout = Ceiling((61.44 MHz × 50 µs)/30) = 103

Synthesizer Lock Timeout

The synthesizer lock timeout ensures that the VCO calibration

DAC, which forces VTUNE, has settled to a steady value for the

band select circuitry.

The timeout and synthesizer lock timeout variables programmed

in Register 9 select the length of time the DAC is allowed to

settle to the final voltage before the VCO calibration process

continues to the next phase, which is VCO band selection. The

PFD frequency is used as the clock for this logic, and the

duration is set by

Frequency

PFD

Timeout

Lock

Synthesize

Timeout ×

The calculated time must be equal to or greater than 20 µs.

VCO Band Selection

Use the PFD frequency again as the clock for the band selection

process. Calculate this value by

PFD/(VCO Band Selection × 16) < 150 kHz

The band selection takes 11 cycles of the previously calculated

value. Calculate the duration by

11 × (VCO Band Selection × 16)/PFD Frequency

Automatic Level Calibration Timeout

Use the automatic level calibration (ALC) function to choose

the correct bias current in the ADF4355 VCO core. Calculate

the time taken by

5 × 11 × ALC Wait × Timeout/PFD Frequency

PLL Low-Pass Filter Settling Time

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth. The settling time is also modeled

in the ADIsimPLL design tool.

The total lock time for changing frequencies is the sum of the

four separate times (synthesizer lock, VCO band selection, ALC

timeout, and PLL settling time) and is all modeled in the

ADIsimPLL design tool.

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