ADF4355

Data Sheet

Rev. A | Page 22 of 35

RD2

REFERENCE

DOUBLER

0DISABLED

1ENABLED

RD1

REFERENCE DIVIDE BY 2

0DISABLED

1ENABLED

CP4CP3CP2CP1

ICP (mA)

5.1kΩ

00

00

0.31

00

01

0.63

00

10

0.94

00

11

1.25

01

00

1.56

01

01

1.88

01

10

2.19

01

11

2.50

10

00

2.81

10

01

3.13

10

10

3.44

10

11

3.75

11

00

4.06

11

01

4.38

11

10

4.69

11

11

5.00

R10

R9

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

R2

R1

R DIVIDER (R)

00

0

1

1

00

1

0

2

..

.

.

.

..

.

.

.

..

.

.

.

1

1

0

0

1020

1

1

0

1

1021

1

1

1

0

1022

1

1

1

1

1023

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

0

0

M3

M2

M1

RD2

RD1

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4

CP3

CP2

CP1

U6

U5

U4

U3

U2

U1

C3(1) C2(0) C1(0)

CURRENT

SETTING

10-BIT R COUNTER

CONTROL

BITS

MUXOUT

U5

LDP

01.8V

13.3V

U4

PD POLARITY

0NEGATIVE

1POSITIVE

U3

POWER DOWN

0DISABLED

1ENABLED

U2

CP

THREE-STATE

0DISABLED

1ENABLED

U1

COUNTER

RESET

0DISABLED

1ENABLED

D1

DOUBLE BUFFERED

REGISTER 6, BITS[DB23:DB21]

0DISABLED

1ENABLED

U6

REFIN

0SINGLE

1DIFF

M3

M2

M1

OUTPUT

0

0

0

THREE-STATE OUTPUT

00

1

01

0

0

1

1

R DIVIDER OUTPUT

1

0

0

N DIVIDER OUTPUT

1

0

1

ANALOG LOCK DETECT

1

1

0

DIGITAL LOCK DETECT

11

1

RESERVED

DB0

C4(0)

RESERVED

Figure 34. Register 4

REGISTER 4

Control Bits

With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 34

shows the input data format for programming this register.

Reserved

Bits[DB31:DB30] are reserved and must be set to 0.

MUXOUT

The on-chip multiplexer (MUXOUT) is controlled by

Bits[DB29:DB27]. For additional details, see Figure 34.

Reference Doubler

to the 10-bit R counter, disabling the doubler. Setting this bit to

1 multiplies the reference frequency by a factor of 2 before feeding

falling edge is the active edge at the PFD input to the fractional

synthesizer. When the doubler is enabled, both the rising and

falling edges of the reference frequency become active edges at

the PFD input.

The maximum allowable reference frequency when the doubler

is enabled is 100 MHz.

RDIV2

Setting the RD1 bit (Bit DB25) to 1 inserts a divide by 2 toggle

flip-flop between the R counter and PFD, which extends the

maximum reference frequency input rate. This function provides

a 50% duty cycle signal at the PFD input.

10-Bit R Counter

The 10-bit R counter divides the input reference frequency

ratios range from 1 to 1023.

Double Buffer

The D1 bit (Bit DB14) enables or disables double buffering of

the RF divider select bits (Bits[DB23:DB21]) in Register 6. The

Program Modes section explains how double buffering works.

Charge Pump Current Setting

The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump

current. Set this value to the charge pump current that the loop

filter is designed with (see Figure 34). For the lowest spurs, the

0.9 mA setting is recommended.