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ADF4355BCPZ датащи(PDF) 30 Page - Analog Devices

номер детали ADF4355BCPZ
подробное описание детали  Analog and digital lock detect
PDF  36 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADF4355BCPZ датащи(HTML) 30 Page - Analog Devices

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Data Sheet
ADF4355
Rev. A | Page 29 of 35
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
P13
P12
P11
P10
P9
RESYNC CLOCK
CONTROL
BITS
P8
P7
P6
P5
P4
P3
P2
P1
0
0
0
00100
0001
C3(1) C2(0) C1(0)
C4(1)
P14
P15
P16
P16
P15
...
P5P4P3P2P1
RESYNC CLOCK
00
...
00
000
NOT ALLOWED
00
...
00
001
1
00
...
00
010
2
.
.
...
.
....
...
00
...
10
110
22
00
...
10
111
23
00
...
11
000
24
.
.
...
.
....
...
11
...
11
101
65533
11
...
11
110
65534
11
...
11
111
65535
RESERVED
Figure 42. Register 12
REGISTER 12
Control Bits
With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 42
shows the input data format for programming this register.
Phase Resync Clock Divider Value
P16 to P1 (Bits[DB31:DB16]) set the timeout counter for
activation of phase resync. This value must be set such that a
resync happens immediately after (and not before) the PLL has
achieved lock after reprogramming.
Calculate the timeout value using the following equation:
Time Out Value = Phase Resync Clock/PFD Frequency
Reserved
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set
to 1, but all other bits in this range must be set to 0.
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, registers must be programmed in sequence. For
fPFD ≤ 75 MHz, use the following sequence:
1.
Register 12.
2.
Register 11.
3.
Register 10.
4.
Register 9.
5.
Register 8.
6.
Register 7.
7.
Register 6.
8.
Register 5.
9.
Register 4.
10. Register 3.
11. Register 2.
12. Register 1.
13. Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs.
See the Register 10 section for more information.
14. Register 0.
For fPFD > 75 MHz (initially lock with half fPFD), use the
following sequence:
1.
Register 12.
2.
Register 11.
3.
Register 10.
4.
Register 9.
5.
Register 8.
6.
Register 7.
7.
Register 6.
8.
Register 5.
9.
Register 4 (with the R divider doubled to output half fPFD).
10. Register 3.
11. Register 2 (for halved fPFD).
12. Register 1 (for halved fPFD).
13. Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.
See the Register 10 section for more information.
14. Register 0 (for halved fPFD; autocalibration enabled).
15. Register 4 (with the R divider set for desired fPFD).
16. Register 2 (for desired fPFD).
17. Register 1 (for desired fPFD).
18. Register 0 (for desired fPFD; autocalibration disabled).
FREQUENCY UPDATE SEQUENCE
Frequency updates require updating the auxiliary modulator
(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,
and the integer value (INT) in Register 0. It is recommended to
perform a temperature dependent VTUNE calibration by updating
Register 10 first. A counter reset (Bit DB4) is also required in
the frequency update sequence Therefore, for fPFD ≤ 75 MHz,
use the following sequence:
1.
Register 10.
2.
Register 4 (counter reset enabled [DB4 = 1]).
3.
Register 2.
4.
Register 1.
5.
Register 0 (autocalibration disabled [DB21 = 0]).
6.
Register 4 (counter reset disabled [DB4 = 0]).



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