ADF4355BCPZ datasheet(15/36 Pages) AD

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ADF4355

Data Sheet

Rev. A | Page 14 of 35

For example, to ensure that the modulus value loads correctly,

every time the modulus value updates, Register 0 must be

written to. The RF divider select in Register 6 is also double

buffered, but only when Bit DB14 of Register 4 is high.

VCO

The VCO core in the ADF4355 consists of four separate VCOs,

each of which uses 256 overlapping bands, which allows covering

a wide frequency range without a large VCO sensitivity (KV) and

without resultant poor phase noise and spurious performance.

The correct VCO and band are chosen automatically by the

VCO and band select logic when Register 0 is updated and auto-

calibration is enabled. The VCO VTUNE is disconnected from

the output of the loop filter and is connected to an internal

reference voltage.

The R counter output is used as the clock for the band select logic.

After band selection, normal PLL action resumes. The nominal

value of KV is 15 MHz/V when the N divider is driven from the

VCO output, or the KV value is divided by D. D is the output

divider value if the N divider is driven from the RF output divider

(chosen by programming Bits[D23:D21] in Register 6).

The VCO shows variation of KV as the tuning voltage, VTUNE,

varies within the band and from band to band. For wideband

applications covering a wide frequency range (and changing

output dividers), a value of 15 MHz/V provides the most accurate

KV, because this value is closest to the average value. Figure 26

shows how KV varies with fundamental VCO frequency along with

an average value for the frequency band. Users may prefer this

figure when using narrow-band designs.

FREQUENCY (GHz)

3.3

3.8

4.3

4.8

5.3

5.8

6.3

6.8

AVERAGE

VCO SENSITIVITY

LINEAR

TREND LINE

Figure 26. KV vs. Frequency

OUTPUT STAGE

The RFOUTA+ and RFOUTA− pins of the ADF4355 connect to

the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 27. In this scheme, the

ADF4355 contains internal 50 Ω resistors connected to the VRF pin.

To optimize the power dissipation vs. the output power requirements,

the tail current of the differential pair is programmable using

Bits[D2:D1] in Register 6. Four current levels can be set. These

levels give approximate output power levels of −4 dBm, −1 dBm,

+2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to VRF

and ac coupling into a 50 Ω load. For accurate power levels,

refer to the Typical Performance Characteristics section. With

an output power of 5 dBm, an external shunt inductor is necessary

to provide higher power levels; however, this addition results in

less wideband than the internal bias only. Terminate the unused

complementary output with a similar circuit to the used output.

VCO

RFOUTA+

RFOUTA–

VRF

50Ω

BUFFER/

DIVIDE BY

1/2/4/8/

16/32/64

Figure 27. Output Stage

Another feature of the ADF4355 is that the supply current to the

output stages can shut down until the ADF4355 achieves lock as

measured by the digital lock detect circuitry. The mute till lock

detect (MTLD) bit (DB11) in Register 6 enables this.

The RFOUTB+/RFOUTB− pins are duplicate outputs that can be

used independently or in addition to the RFOUTA+/RFOUTA− pins.

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