SC16C652 datasheet(23/41 Pages) PHILIPS

23 / 41 page

Philips Semiconductors

SC16C652

Dual UART with 32 bytes of transmit and receive FIFOs

Product data

Rev. 04 — 20 June 2003

23 of 41

9397 750 11634

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C652 and

the CPU.

Table 21:

Line Status Register bits description

Bit

Symbol

Description

LSR[7]

FIFO data error.

Logic 0 = No error (normal default condition).

Logic 1 = At least one parity error, framing error or break

indication is in the current FIFO data. This bit is cleared when

there are no remaining error ﬂags associated with the remaining

data in the FIFO.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This

bit is set to a logic 1 whenever the transmit holding register and the

transmit shift register are both empty. It is reset to logic 0 whenever

either the THR or TSR contains a data character. In the FIFO

mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit

shift register are both empty.

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty

indicator. This bit indicates that the UART is ready to accept a new

character for transmission. In addition, this bit causes the UART to

issue an interrupt to CPU when the THR interrupt enable is set.

The THR bit is set to a logic 1 when a character is transferred from

the transmit holding register into the transmitter shift register. The

bit is reset to a logic 0 concurrently with the loading of the

transmitter holding register by the CPU. In the FIFO mode, this bit

is set when the transmit FIFO is empty; it is cleared when at least

1 byte is written to the transmit FIFO.

LSR[4]

Break interrupt.

Logic 0 = No break condition (normal default condition).

Logic 1 = The receiver received a break signal (RX was a logic 0

for one character frame time). In the FIFO mode, only one break

character is loaded into the FIFO.

LSR[3]

Framing error.

Logic 0 = No framing error (normal default condition).

Logic1=Framing error. The receive character did not have a

valid stop bit(s). In the FIFO mode, this error is associated with

the character at the top of the FIFO.

LSR[2]

Parity error.

Logic 0 = No parity error (normal default condition.

Logic1=Parity error. The receive character does not have

correct parity information and is suspect. In the FIFO mode, this

error is associated with the character at the top of the FIFO.

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