SC16C652 datasheet(16/41 Pages) PHILIPS

16 / 41 page

Philips Semiconductors

SC16C652

Dual UART with 32 bytes of transmit and receive FIFOs

Product data

Rev. 04 — 20 June 2003

16 of 41

9397 750 11634

7.2.1

IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)

are enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit

and the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred

from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is

empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated

when the transmit FIFO is empty due to the unloading of the data by the TSR and

UART for transmission via the transmission media. The interrupt is cleared either

by reading the ISR register, or by loading the THR with new data characters.

IER[2]

Receive Line Status interrupt. This interrupt will be issued

whenever a receive data error condition exists as reﬂected in

LSR[1-4].

Logic 0 = Disable the receiver line status interrupt (normal

default condition).

Logic 1 = Enable the receiver line status interrupt.

IER[1]

Transmit Holding Register interrupt. In the 16C450 mode, this

interrupt will be issued whenever the THR is empty, and is

associated with LSR[5]. In the FIFO modes, this interrupt will be

issued whenever the FIFO is empty.

Logic 0 = Disable the Transmit Holding Register Empty (TXRDY)

interrupt (normal default condition).

Logic 1 = Enable the TXRDY (ISR level 3) interrupt.

IER[0]

Receive Holding Register. In the 16C450 mode, this interrupt will

be issued when the RHR has data, or is cleared when the RHR is

empty. In the FIFO mode, this interrupt will be issued when the

FIFO has reached the programmed trigger level or is cleared when

the FIFO drops below the trigger level.

Logic 0 = Disable the receiver ready (ISR level 2, RXRDY)

interrupt (normal default condition).

Logic 1 = Enable the RXRDY (ISR level 2) interrupt.

Table 10:

Interrupt Enable Register bits description…continued

Bit

Symbol

Description

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