SC16C652 datasheet(8/41 Pages) PHILIPS

8 / 41 page

Philips Semiconductors

SC16C652

Dual UART with 32 bytes of transmit and receive FIFOs

Product data

Rev. 04 — 20 June 2003

8 of 41

9397 750 11634

6.2 Internal registers

The SC16C652 provides two sets of internal registers (A and B) consisting of

12 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data

holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO

control register (FCR), line status and control registers (LCR/LSR), modem status

and control registers (MCR/MSR), programmable data rate (clock) control registers

(DLL/DLM), and a user accessible scratchpad register (SPR).

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

[3]

Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to

‘BF(HEX)’.

6.3 FIFO operation

The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control

level, but not the transmit trigger level. The SC16C652 provides independent trigger

levels for both receiver and transmitter. To remain compatible with SC16C2550, the

transmit interrupt trigger level is set to 16 following a reset. It should be noted that the

user can set the transmit trigger levels by writing to the FCR register, but activation

will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes

a time-out function to ensure data is delivered to the external CPU. An interrupt is

generated whenever the Receive Holding Register (RHR) has not been read

following the loading of a character or the receive trigger level has not been reached.

Table 4:

Internal registers decoding

READ mode

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)[2]

LSB of Divisor Latch

MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)[3]

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

SC16C652 датащи(PDF) 8 Page - NXP Semiconductors

SC16C652 датащи(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

датащи скачать

ссылки URL