SC16C652 datasheet(9/41 Pages) PHILIPS

9 / 41 page

Philips Semiconductors

SC16C652

Dual UART with 32 bytes of transmit and receive FIFOs

Product data

Rev. 04 — 20 June 2003

9 of 41

9397 750 11634

6.4 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C652 monitors the CTS

pin for a remote buffer overﬂow indication and controls the RTS pin for local buffer

overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and

EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a

ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the

SC16C652 will suspend TX transmissions as soon as the stop bit of the character in

process is shifted out. Transmission is resumed after the CTS input returns to a

logic 0, indicating more data may be sent.

With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1

(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin

will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level

below the programmed trigger level. However, under the above described conditions,

the SC16C652 will continue to accept data until the receive FIFO is full.

6.5 Software ﬂow control

When software ﬂow control is enabled, the SC16C652 compares one or two

sequential receive data characters with the programmed Xon or Xoff character

value(s). If received character(s) match the programmed Xoff values, the SC16C652

will halt transmission (TX) as soon as the current character(s) has completed

transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5])

ﬂags will be set and the interrupt output pin (if receive interrupt is enabled) will be

activated. Following a suspension due to a match of the Xoff characters’ values, the

SC16C652 will monitor the receive data stream for a match to the Xon1,2 character

value(s). If a match is found, the SC16C652 will resume operation and clear the ﬂags

(ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow

control. Different conditions can be set to detect Xon/Xoff characters and

suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,

the SC16C652 compares two consecutive receive characters with two software ﬂow

control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions

accordingly. Under the above described ﬂow control mechanisms, ﬂow control

characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

When using a software ﬂow control the Xon/Xoff characters cannot be used for data

transfer.

Table 5:

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

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