SC16C652 datasheet(18/41 Pages) PHILIPS

18 / 41 page

Philips Semiconductors

SC16C652

Dual UART with 32 bytes of transmit and receive FIFOs

Product data

Rev. 04 — 20 June 2003

18 of 41

9397 750 11634

7.3.2

FIFO mode

Table 11:

FIFO Control Register bits description

Bit

Symbol

Description

7-6

FCR[7]

(MSB),

FCR[6]

(LSB)

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Table 12.

5-4

FCR[5]

(MSB),

FCR[4]

(LSB)

Logic 0 or cleared is the default condition; TX trigger level = 16.

These bits are used to set the trigger level for the transmit FIFO

interrupt. The SC16C652 will issue a transmit empty interrupt when the

number of characters in FIFO drops below the selected trigger level.

Refer to Table 13.

FCR[3]

DMA mode select.

Logic 0 = Set DMA mode ‘0’ (normal default condition).

Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C652 is in the 16C450

mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs

enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no

characters in the transmit FIFO or transmit holding register, the TXRDY

pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after

the ﬁrst character is loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC16C652 is in 16C450

mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and

there is at least one character in the receive FIFO, the RXRDY pin will

be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there

are no more characters in the receiver.

Transmit operation in mode ‘1’: When the SC16C652 is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1

when the transmit FIFO is completely full. It will be a logic 0 when the

trigger level has been reached.

Receive operation in mode ‘1’: When the SC16C652 is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been

reached, or a Receive Time-Out has occurred, the RXRDY pin will go to

a logic 0. Once activated, it will go to a logic 1 after there are no more

characters in the FIFO.

FCR[2]

XMIT FIFO reset.

Logic 0 = No FIFO transmit reset (normal default condition).

Logic 1 = Clears the contents of the transmit FIFO and resets the

FIFO counter logic (the transmit shift register is not cleared or

altered). This bit will return to a logic 0 after clearing the FIFO.

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