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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC16C652 датащи(PDF) 19 Page - NXP Semiconductors |
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SC16C652 датащи(HTML) 19 Page - NXP Semiconductors |
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19 / 41 page  Philips Semiconductors SC16C652 Dual UART with 32 bytes of transmit and receive FIFOs Product data Rev. 04 — 20 June 2003 19 of 41 9397 750 11634 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 1 FCR[1] RCVR FIFO reset. Logic 0 = No FIFO receive reset (normal default condition). Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO. This bit must be a ‘1’ when other FCR bits are written to, or they will not be programmed. Table 12: RCVR trigger levels FCR[7] FCR[6] RX FIFO trigger level (bytes) 008 0116 1024 1128 Table 13: TX FIFO trigger levels FCR[5] FCR[4] TX FIFO trigger level (bytes) 0016 018 1024 1130 Table 11: FIFO Control Register bits description…continued Bit Symbol Description |
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