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ADPD103

Data Sheet

Rev. B | Page 30 of 52

Measuring TIA Input Shunt Resistance

Another problem that can occur is for a resistance to develop

between the TIA input and another supply or ground on the

PCB. These resistances can force the TIA into saturation

prematurely. This, in turn, takes away dynamic range from the

device in operation and adds a Johnson noise component to the

input. To measure these resistances, place the device in TIA_ADC

mode in the dark and start by measuring the TIA_ADC offset level

with the photodiode inputs disconnected (Register 0x14,

Bits[11:8] = 0 or Register 0x14, Bits[7:4] = 0). From this,

subtract the value of TIA_ADC mode with the darkened

photodiode connected and convert the difference into a current.

If the value is positive, and the ADC signal decreased, the

resistance is to a voltage higher than 1.3 V, such as VDD. Current

entering the TIA causes the output to drop. If the output

difference is negative due to an increase of codes at the ADC,

current is being pulled out of the TIA and there is a shunt

resistance to a lower potential than 1.3 V, such as ground.

DIGITAL INTEGRATE MODE

Digital integrate mode is built into the ADPD103 and allows the

device to accommodate longer LED/AFE pulse widths and

different types of sensors at the input. The analog integration

mode described in the AFE Operation section is ideally suited

for applications requiring a large LED duty cycle, or applications

that require customization of the sampling scheme. Digital

integrate mode allows the integration function to be performed

after the ADC in the digital domain. This mode enables the

device to handle a much wider range of sensors at the input.

In digital integrate mode, the ADC performs a conversion every

1 µs during the integration window. During the integration

window, the digital engine either adds to or subtracts from the

previous sample. The band-pass filter is bypassed and the

integrator is converted to a voltage buffer, allowing the digital

engine to perform the integration function. In this mode, after

the timing is optimized, the output of the ADC increases as the

light level on the photodiode increases.

The integration window is a combination of negative and positive

windows where the duration of these windows is set by SLOTx_

AFE_WIDTH. At the end of the digital integration window, the

resulting sum is sent to the decimate unit as the sample for that

LED pulse. There is one sample per time slot for every sample

cycle. Table 18 lists the registers required for placing the device

in digital integrate mode.

There may also be changes needed in the SLOTx_AFE_OFFSET

registers and FIFO configuration register (0x11). To read the

final value through the FIFO, set the appropriate values in Regis-

ter 0x11, Bits[4:2] for Time SlotA, and Register 0x11, Bits[8:6]

for Time Slot B. Alternatively, the final output is also available

through the data registers; Register 0x64, Register 0x70, and

and Register 0x7C for Time Slot B.

To put the ADPD103 into digital integration mode during Time

Slot A, write 0x1 to Register 0x58, Bit 12. To put the ADPD103

into digital integration mode in Time Slot B, write 0x1 to

digital integration mode are listed in Table 18.

When using digital integrate mode, up to two photodiodes can

be connected to the ADPD103 inputs; one photodiode per PDx

input group (PD1/PD2/PD3/PD4 or PD5/PD6/PD7/PD8).

Never connect the same photodiode across the two PDx groups.

In digital integrate mode, there are options to connect the

photodiode to all fourAFE channels (PD1/PD2/PD3/PD4 or

PD5/PD6/PD7/PD8), or just a single AFE channel (PD1 or

PD5). When connecting to a single AFE channel, write 0x1 to

0x1 to Register 0x54, Bit 15.

When connecting to a single AFE channel, there is also an

option to turn off Channel 2, Channel 3, and Channel 4 (and to

save power) by writing 0x7 to Register 0x55, Bits[15:13]. When

connecting to all four channels (PD1/PD2/PD3/PD4 or

PD5/PD6/PD7/PD8), write 0x0 (default)to Register 0x54, Bit 14

for Time Slot A, or write 0x0 (default) to Register 0x54, Bit 15

for Time Slot B. Ensure that all AFE channels are powered up by

writing 0x0 to Register 0x55, Bits[15:13].

Connecting the single photodiode to a singleAFE channel offers

the best SNR performance in cases where signal is limited, whereas

connecting the single photodiode to all four AFE channels offers

the best dynamic range in cases where signal is large.

Digital Integration Sampling Modes

There are two sampling modes that can be used while the

device is in digital integration mode. These modes are single-

sample pair mode and double-sample pair mode.

In single-sample pair mode, there is a single negative sample

region and a single positive sample region, shown in Figure 29

and Figure 30. To use single-sample pair mode, write 0x1 to

Time Slot B. The negative sample region starts at SLOTx_AFE_

OFFSET + 9 and its duration (the number of samples taken) is set

by SLOTx_AFE_WIDTH. The positive sample region starts at

SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH, and its

duration is also set by SLOTx_AFE_WIDTH. Set the timing

such that the negative sample region falls entirely in the flat

(dark) portion of the LED response, whereas the positive

sample region falls in the pulsed region of the LED response.

Placing the LED pulse offset, SLOTx_LED_OFFSET, at the

beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH

achieves this timing. The output is the difference of the signals

in the two regions.

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