ADPD103 datasheet(34/53 Pages) AD

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Data Sheet

ADPD103

Rev. B | Page 33 of 52

Table 18. Configuration Registers to Switch Between the Normal Sample Mode, TIA_ADC Mode, and Digital Integration Mode

Address

Data

Bits

Bit Name

Normal

Mode

Value

TIA_ADC

Mode Value

Digital

Integration

Mode Value

Description

0x42

[15:8]

SLOTA_AFE_MODE

0x1C

Not applicable

0x1D

In normal mode, this setting configures the

integrator block for optimal operation. In

digital integration mode, this setting

configures the integrator block as a buffer.

This setting is not important for TIA_ADC

mode.

0x43

[15:0]

SLOTA_AFE_CFG

0xADA5

0xB065

0xAE65

Time Slot AAFE connection.

0xAE65 bypasses the band-pass filter.

0xB065 bypasses the band-pass filter and

the integrator.

0x44

[15:8]

SLOTB_AFE_MODE

0x1C

Not applicable

0x1D

In normal mode, this setting configures the

integrator block for optimal operation. In

digital integration mode, this setting

configures the integrator block as a buffer.

This setting is not important for TIA_ADC

mode.

0x45

[15:0]

SLOTB_AFE_CFG

0xADA5

0xB065

0xAE65

Time Slot B AFE connection.

0xAE65 bypasses the band-pass filter.

0xB065 bypasses the BPF and the integrator.

0x4E

[15:0]

ADC_TIMING

Not

applicable

Not applicable

0x0040

Set ADC Clock to 1 MHz in TIA_ADC mode.

0x58

SLOTB_DIGITAL_INT_EN

0x0

0x1

Digital integrate mode enable Time Slot B.

0: disable.

1: enable.

SLOTA_DIGITAL_INT_EN

0x0

0x1

Digital integrate mode enable Time Slot A.

0: disable.

1: enable.

0x5A

[15:0]

DIG_INT_CFG

Not

applicable

Not applicable

Variable

Configuration of digital integration depends

on the use case. This register is ignored for

other modes.

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