ADPD103 datasheet(16/53 Pages) AD

16 / 53 page

Data Sheet

ADPD103

Rev. B | Page 15 of 52

Table 13. Time Slot Switch (Register 0x14)

Address

Bits

Name

Description

0x14

[11:8]

SLOTB_PD_SEL

Selects connection of photodiode for Time Slot B as shown in Figure 11, Figure 12,

and Figure 13.

0x0: inputs are floating in Time Slot B.

0x1: all PDx pins (PD1 to PD8) are connected during Time Slot B.

0x4: PD5 to PD8 are connected during Time Slot B.

0x5: PD1 to PD4 are connected during Time Slot B.

Other: reserved.

[7:4]

SLOTA_PD_SEL

Selects connection of photodiode for Time Slot A as shown in Figure 11, Figure 12,

and Figure 13.

0x0: inputs are floating in Time Slot A.

0x1: All PDx pins (PD1 to PD8) are connected during Time Slot A.

0x4: PD5 to PD8 are connected during Time Slot A.

0x5: PD1 to PD4 are connected during Time Slot A.

Other: reserved.

ADJUSTABLE SAMPLING FREQUENCY

ADPD103 and Register 0x4B, Bits[5:0] further tunes this clock

for greater accuracy. The sampling frequency is governed by an

internal 32 kHz sample rate clock that also drives the transition

of the internal state machine. The maximum sampling frequencies

for some sample conditions are listed in Table 3. The maximum

sample frequency for all conditions is determined by the

following equation:

fSAMPLE, MAX = 1/(tA + t1 + tB + t2 + tSLEEP, MIN)

If a given time slot is not in use, elements from that time slot do

not factor into the calculation. For example, if Time Slot A is not

in use, tA and t1 do not add to the sampling period and the new

maximum sampling frequency is calculated as follows:

fSAMPLE, MAX = 1/( tB + t2 + tSLEEP,MIN)

where tSLEEP, MIN is the minimum sleep time required between

samples. See the Dual Time Slot Operation section for the

definitions of tA, t1, tB, and t2.

External Sync for Sampling

The ADPD103 provides an option to use an external sync signal

to trigger the sampling periods. This external sample sync signal

can be provided either on the INT pin or the PDSO pin. This

functionality is controlled by Register 0x4F, Bits[3:2]. When

enabled, a rising edge on the selected input specifies when the

next sample cycle occurs. When triggered, there is a delay of one to

two internal sampling clock (32 kHz) cycles, and then the normal

start-up sequence occurs. This sequence is the same as if the

normal sample timer provided the trigger. To enable the external

sync signal feature, use the following procedure:

1. Write 0x1 to Register 0x10 to enter program mode.

2. Write the appropriate value to Register 0x4F, Bits[3:2] to

select whether the INT pin or the PDSO pin specifies when

the next sample cycle occurs. Also, enable the appropriate

input buffer using Register 0x4F, Bit 1, for the INT pin, or

3. Write b1 to EXT_SYNC_ENA, Register 0x38, Bit 14 to

enable the external sampling trigger.

4. Write 0x2 to Register 0x10 to start the sampling operations.

5. Apply the external sync signal on the selected pin at the

desired rate; sampling occurs at that rate. As with normal

sampling operations, read the data using the FIFO or the

data registers.

The maximum frequency constraints also apply in this case.

Providing an External 32kHz Clock

The ADPD103 has an option for the user to provide an external

32 kHz clock to the device for system synchronization or for

situations where a clock with better accuracy than the internal

32 kHz clock is required. The external 32 kHz clock is provided

on the PDSO pin. To enable the 32 kHz external clock, use the

following procedure at startup:

1. Drive the PDSO pin to a valid logic level or with the

desired 32 kHz clock prior to enabling the PDSO pin as an

input. Do not leave the pin floating prior to enabling it.

2. Write b1 to Register 0x4F, Bit 5 to enable the PDSO pin as

an input.

3. Write b11 to register 0x4B, Bit 7 and Bit 8 (CLK32K_EN

and CLK32K_BYP, respectively) to configure the device to

use an external 32 kHz clock.

4. Write 0x1 to Register 0x10 to enter program mode.

5. Write additional control registers in any order while the

device is in program mode to configure the device as

required.

6. Write 0x2 to Register 0x10 to start the normal sampling

operation.

ADPD103 датащи(PDF) 16 Page - Analog Devices

ADPD103 датащи(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

датащи скачать

ссылки URL