ADPD103 datasheet(25/53 Pages) AD

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ADPD103

Data Sheet

Rev. B | Page 24 of 52

The numerator of the CVLED equation sets up the total discharge

amount in coulombs from the bypass capacitor to satisfy a

single programmed LED pulse of the maximum current. The

denominator represents the difference between the lowest voltage

from the VLEDx supply and the LED required voltage. The LED

required voltage is the voltage of the anode of the LED such that

the 0.2 V compliance of the LED driver and the forward-biased

voltage of the LED operating at the maximum current is satisfied.

For a typical ADPD103 example, assume that the lowest value

for the VLEDx supply is 4.4 V, and that the peak current is 250 mA

for two 528 nm LEDs in parallel. The minimum value for CVLED

is then equal to 3 µF.

CVLED = (3 × 10−6 × 0.250)/(4.4 – (3.95 + 0.2)) = 3 µF

(3)

As shown in the Equation 3, as the minimum supply voltage drops

close to the maximum anode voltage, the demands on CVLED

become more stringent, forcing the capacitor value higher. It is

important to insert the correct values into these equations. For

example, using an average value for VLED_MIN instead of the

worst case value for VLED_MIN can cause a serious design deficiency,

resulting in a CVLED value that is too small and that causes

insufficient optical power in the application. Therefore, adding a

sufficient margin on CVLED is strongly recommended. Add

additional margin to CVLED to account for derating of the capacitor

value over voltage, bias, temperature and other factors over the life

of the component.

LED INDUCTANCE CONSIDERATIONS

The LED drivers (LEDXx) on the ADPD103 have configurable

slew rate settings (Register 0x22, Bits[6:4], Register 0x23, Bits[6:4],

and Register 0x24, Bits[6:4]). These slew rates are defined in

Table 3. Even at the lowest setting, careful consideration must be

taken in board design and layout. If a large series inductor, such as a

long PCB trace, is placed between the LED cathode and one of

the LEDXx pins, voltage spikes from the switched inductor can

cause violations of absolute maximum and minimum voltages

on the LEDXx pins during the slew portion of the LED pulse.

To verify that there are no voltage spikes on the LEDXx pins due

to parasitic inductance, use an oscilloscope on the LEDXx pins to

monitor the voltage during normal operation.Any positive spike

>3.6 V may damage the device.

In addition, a negative spike <−0.3 V may also damage the device.

RECOMMENDED START-UP SEQUENCE

At power-up, the device is in standby mode (Register 0x10 =

0x0), as shown in Figure 14. The ADPD103 does not require a

particular power-up sequence.

From standby mode, to begin measurement, initiate the

ADPD103 as follows:

1. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the

sample clock (32 kHz clock). This clock controls the state

machine. If this clock is off, the state machine is not able to

transition as defined by Register 0x10.

2. Write 0x1 to Register 0x10 to force the device into program

mode. Step 1 and Step 2 can be swapped, but the actual

state transition does not occur until both steps occur.

3. Write additional control registers in any order while the

device is in program mode to configure the device as

required.

4. Write 0x2 to Register 0x10 to start normal sampling

operation.

To terminate normal operation, follow this sequence to place

the ADPD103 in standby mode:

1. Write 0x1 to Register 0x10 to force the device into program

mode.

2. Write to the registers in any order while the device is in

program mode.

3. Write 0x00FF to Register 0x00 to clear all interrupts. If

desired, clear the FIFO as well by setting the DIGITAL_

CLOCK_ENA bit (Register 0x5F, Bit 0) and writing 0x80FF

to Register 0x00.

4. Write 0x0 to Register 0x10 to force the device into standby

mode.

5. Optionally, stop the 32 kHz clock by resetting the CLK32K_

EN bit (Register 0x4B, Bit 7). Register 0x4B, Bit 7 = 0 is the

only write that must be written when the device is in standby

mode (Register 0x10 = 0x0). If 0 is written to this bit while in

program mode or normal mode, the device becomes

unable to transition into any other mode, including standby

mode, even if it is subsequently written to do so.As a result,

the power consumption in what appears to be standby mode

is greatly elevated. For this reason, and due to the very low

current draw of the 32 kHz clock while in operation, it is

recommended from an ease of use perspective to keep the

32 kHz clock running after it is turned on.

READING DATA

TheADPD103 provides multiple methods for accessing the sample

data. Each time slot can be independently configured to provide

data access using the FIFO or the data registers. Interrupt signaling

is also available to simplify timely data access. The FIFO is available

to loosen the system timing requirements for data accesses.

Reading Data Using the FIFO

The ADPD103 includes a 128-byte FIFO memory buffer that

can be configured to store data from either or both time slots.

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