ADPD103 datasheet(27/53 Pages) AD

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ADPD103

Data Sheet

Rev. B | Page 26 of 52

indicate when the registers are updated and can be read. To use

the interrupt for a given time slot, use the following procedure:

1. Enable the sample interrupt by writing a 0 to the appropriate

bit in Register 0x01. To enable the interrupt for Time SlotA,

write 0 to Bit 5. To enable the interrupt for Time Slot B,

write 0 to Bit 6. Either or both interrupts can be set.

2. Configure the interrupt pin by writing the appropriate

value to the bits in Register 0x02.

3. An interrupt generates when the data registers are updated.

4. The interrupt handler must perform the following:

a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm

which interrupt has occurred. This step is not required if

only one interrupt is in use.

b. Read the data registers before the next sample can be

written. The system must have interrupt latency and

service time short enough to respond before the next

data update, based on the output data rate.

c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the

interrupt.

If both time slots are in use, it is possible to use only the

Time Slot B interrupt to signal when all registers can be read. It

is recommended to use the multiword read to transfer the data

from the data registers.

Reading Data from Registers Without Interrupts

If the system interrupt response is not fast or predictable

enough to use the interrupt method, or if the interrupt pin is

not used, it is possible to get reliable data access by using the

data hold mechanism. To guarantee that the data read from the

registers is from the same sample time, it is necessary to prevent

the update of samples while reading the current values. The

method for doing register reads without interrupt timing is as

follows:

1. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_

HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the

time slot requiring access (both time slots can be accessed).

This prevents sample updates.

2. Read the registers as desired.

3. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_DATA_

HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively)

previously set. Sample updates are allowed again.

Because a new sample may arrive while the reads are occurring,

this method prevents the new sample from partially overwriting

the data being read.

CLOCKS AND TIMING CALIBRATION

The ADPD103 operates using two internal time bases: a 32 kHz

clock sets the sample timing, and a 32 MHz clock controls the

timing of the internal functions such as LED pulsing and data

capture. Both clocks are internally generated and exhibit device-

to-device variation of approximately 10% (typical).

Heart rate monitoring applications require an accurate time

base to achieve an accurate count of beats per minute. The

ADPD103 provides a simple calibration procedure for both clocks.

1. Calibrating the 32 kHz clock. This calibrates items

associated with the output data rate. Calibration of this

clock is important for applications where an accurate data

rate is important, such as heart rate measurements.

a. Set the sampling frequency to the highest the system

can handle, such as 2000 Hz. Because the 32 kHz clock

controls sample timing, its frequency is readily accessible

via the INT pin. Configure the interrupt by writing the

appropriate value to the bits in Register 0x02 and set the

interrupt to occur at the sampling frequency by writing 0

to Register 0x01, Bit 5 or Bit 6. Monitor the INT pin.

The interrupt frequency must match the set sample

frequency.

b. If the monitored interrupt frequency is less than the set

sampling frequency, increase the CLK32K_ADJUST bit

(Register 0x4B, Bits[5:0]). If the monitored interrupt

frequency is larger than the set sampling frequency,

decrease the CLK32K_ADJUST bits.

c. Repeat Step b until the monitored interrupt signal

frequency is close enough to the set sampling frequency.

2. Calibrate the 32 MHz clock. This calibrates items associated

with the fine timing within a sample period, such as LED

pulse width and spacing, assuming that the 32 kHz clock

has been calibrated.

a. Write 0x1 to Register 0x5F, Bit 0.

b. Enable the CLK_RATIO calculation by writing 0x1 to

32 MHz clock cycles in two cycles of the 32 kHz clock.

With this function enabled, this cycle value is stored in

(0x7D0).

c. Calculate the 32 MHz clock error as follows:

Clock Error = 32 MHz × (1 − CLK_RATIO/2000)

d. Adjust the frequency by setting Bits[7:0] in Register

0x4D per the following equation:

CLK32M_ADJUST = Clock Error/109 kHz

e. Write 0x0 to Register 0x50, Bit 5 to reset the

CLK_RATIO function.

Repeat Step 2b through Step 2e until the desired accuracy is

achieved.

Write 0x0 to Register 0x5F, Bit 0. Also, set the INT pin back to

the mode desired for normal operation.

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