ADPD103 datasheet(43/53 Pages) AD

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ADPD103

Data Sheet

Rev. B | Page 42 of 52

Address

Data Bit

Default

Value

Access

Name

Description

0x58

[15:14]

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

SLOTB_DIGITAL_INT_EN

0x0: Time Slot B operating in normal mode.

0x1: Time Slot B operating in digital integration mode.

0x0

R/W

SLOTA_DIGITAL_INT_EN

0x0: Time Slot A operating in normal mode.

0x1: Time Slot A operating in digital integration mode.

[11:0]

0x000

R/W

Reserved

Write 0x000.

0x5A

[15:8]

0x00

R/W

Reserved

Write 0x00.

0x0

R/W

DIG_INT_GAPMODE

Digital integrate gapped mode enable.

0: no gap between negative and positive sample regions.

1: use SLOTA_AFE_FOFFSET for Time SlotA or SLOTB_AFE_

FOFFSET for Time Slot B to specify the gap in μs.

0x0

R/W

SLOTB_DIG_INT_SAMPLE_MODE Digital integrate single sample pair mode for Time Slot B.

0: double sample pair mode.

1: single sampled pair mode.

0x0

R/W

SLOTA_DIG_INT_SAMPLE_MODE

Digital integrate single sample pair mode for Time Slot A.

0: double sample pair mode.

1: single sampled pair mode.

[4:0]

0x00

R/W

Reserved

Write 0x00.

Table 22. AFE Configuration Registers, Time Slot A

Address

Data

Bit

Default

Value

Access Name

Description

0x39

[15:11]

0x4

R/W

SLOTA_AFE_WIDTH

AFE integration window width (in 1 μs step) for Time Slot A.

[10:5]

0x17

R/W

SLOTA_AFE_OFFSET

AFE integration window coarse offset (in 1 μs step) for

Time Slot A.

[4:0]

0x1C

R/W

SLOTA_AFE_FOFFSET

AFE integration window fine offset (in 31.25 ns step) for

Time Slot A.

0x42

[15:8]

0x1C

R/W

SLOTA_AFE_MODE

0x1C: Time Slot AAFE setting for normal mode. All four blocks

of the signal chain are in use during normal mode (the TIA,

the BPF, followed by the integrator (INT), and finally the ADC).

0x1D: Time Slot AAFE setting for digital integrate mode.

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

SLOTA_TIA_IND_EN

Enable Time Slot ATIA gain individual settings. When it is

enabled, the Channel 1 TIA gain is set via Register 0x42,

Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set

via Register 0x55, Bits[5:0].

0: disable TIA gain individual setting.

1: enable TIA gain individual setting.

[5:2]

0xE

R/W

Reserved

Reserved. Write 0xD.

[1:0]

0x0

R/W

SLOTA_TIA_GAIN

Transimpedance amplifier gain for Time Slot A. When

SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B,

Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is

for all four Time Slot A channel TIA gain settings.

0: 200 kΩ.

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

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