ADPD103 datasheet(48/53 Pages) AD

48 / 53 page

Data Sheet

ADPD103

Rev. B | Page 47 of 52

Address

Data

Bit

Default Access Name

Description

0x09

[15:8]

0x0

ADDRESS_WRITE_KEY Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access.

[7:1]

0x64

R/W

SLAVE_ADDRESS

I2C slave address.

0x0

Reserved

Do not access.

0x0A

[15:12]

0x0

Reserved

Reserved. Read only.

[11:0]

0x000

CLK_RATIO

When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device

calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz

clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits.

0x0D

[15:0]

0x0

R/W

SLAVE_ADDRESS_KEY

Enable changing the I2C address using Register 0x09.

0x04AD: enable address change always.

0x44AD: enable address change if INT is high.

0x84AD: enable address change if PDSO is high.

0xC4AD: enable address change if both INT and PDSO are high.

0x0F

[15:1]

0x0000

Reserved

Reserved. Read only.

0x0

R/W

SW_RESET

Software reset. Write 0x1 to reset the device. This bit clears itself after a

reset. This command does not return an acknowledge because the

command is instantaneous.

0x10

[15:2]

0x000

R/W

Reserved

Write 0x000.

[1:0]

0x0

R/W

Mode

Determines the operating mode of the ADPD103.

0x0: standby.

0x1: program.

0x2: normal operation.

0x11

[15:14]

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

RDOUT_MODE

Readback data mode for extended data registers

0x0: Block sum of N samples

0x1: Block average of N samples

0x1

R/W

FIFO_OVRN_PREVENT

0x0: wrap around FIFO, overwriting old data with new.

0x1: new data if FIFO is not full (recommended setting).

[11:9]

0x0

R/W

Reserved

Write 0x0.

[8:6]

0x0

R/W

SLOTB_FIFO_MODE

Time Slot B FIFO data format.

0: no data to FIFO.

1: 16-bit sample in digital integration mode or 16-bit sum of all

4 channels when not in digital integration mode.

2: 32-bit sample in digital integration mode or 32-bit sum of all

4 channels when not in digital integration mode.

3: 16-bit sample and 16-bit background value in digital integration mode

4: 32-bit sample and 32-bit background value in digital integration

mode or 4 channels of 16-bit sample data for Time Slot B when not in

digital integration mode.

6: 4 channels of 32-bit extended sample data for Time Slot B when not in

digital integration mode.

Others: reserved.

The selected Time Slot B data is saved in the FIFO. Available only if Time

Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] = Bits[6:4]),

or if Time SlotA is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0).

0x0

R/W

SLOTB_EN

Time Slot B enable. 1: enables Time Slot B.

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