ADPD103 datasheet(17/53 Pages) AD

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ADPD103

Data Sheet

Rev. B | Page 16 of 52

STATE MACHINE OPERATION

During each time slot, the ADPD103 operates according to a

state machine. The state machine operates in the following

sequence, shown in Figure 14.

STANDBY

ULTRALOW POWER MODE

NO DATA COLLECTION

ALL REGISTER VALUES ARE RETAINED.

PROGRAM

SAFE MODE FOR PROGRAMING REGISTERS

NO DATA COLLECTION

DEVICE IS FULLY POWERED IN THIS MODE.

NORMAL OPERATION

LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED

STANDARD DATA COLLECTION

DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE.

Figure 14. State Machine Operation Flowchart

The ADPD103 operates in one of three modes: standby,

program, and normal sampling mode.

Standby mode is a power saving mode in which no data collection

occurs. All register values are retained in this mode. To place

the device in standby mode, write 0x0 to Register 0x10,

Bits[1:0]. The device powers up in standby mode.

Program mode is used for programming registers. Always cycle

the ADPD103 through program mode when writing registers or

changing modes. Because no power cycling occurs in this mode,

the device may consume higher current in program mode than

in normal operation. To place the device in program mode,

write 0x1 to Register 0x10, Bits[1:0].

In normal operation, the ADPD103 pulses light and collects

data. Power consumption in this mode depends on the pulse

count and data rate. To place the device in normal sampling

mode, write 0x2 to Register 0x10, Bits[1:0].

NORMAL MODE OPERATION AND DATA FLOW

In normal mode, theADPD103 follows a specific pattern set up by

the state machine. This pattern is shown in the corresponding data

flow in Figure 15. The pattern is as follows:

1. LED pulse and sample.TheADPD103 pulses external LEDs.

The response of a photodiode or photodiodes to the reflected

light is measured by theADPD103. Each data sample is

constructed from the sum of n individual pulses, where n

is user configurable between 1 and 255.

2. Intersample averaging. If desired, the logic can average n

samples, from 2 to 128 in powers of 2, to produce output

data. New output data is saved to the output registers every

N samples.

3. Data read. The host processor reads the converted results

from the data register or the FIFO.

4. Repeat. The sequence has a few different loops that enable

different types of averaging while keeping both time slots

close in time relative to each other.

SAMPLE 1: TIME SLOT B

16 BITS

[14 + LOG2(nA)] BITS

UP TO 20 BITS

[14 + LOG2(nA × NA)] BITS

UP TO 27 BITS

[14 + LOG2(nB × NB)] BITS

UP TO 27 BITS

TIME SLOT B

TIME SLOT A

16-BIT CLIP

IF VAL ≤ (216 – 1)

VAL = VAL

ELSE VAL = 216 – 1

NOTES

1. nA AND nB = NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B.

2. NA AND NB = NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B.

16 BITS

[14 + LOG2(nB)] BITS

UP TO 20 BITS

16-BIT CLIP

IF VAL ≤ (216 – 1)

VAL = VAL

ELSE VAL = 216 – 1

ADC OFFSET

[14 + LOG2(nA)] BITS

UP TO 22 BITS

SAMPLE 1: TIME SLOT A

SAMPLE NB: TIME SLOT B

SAMPLE NA: TIME SLOT A

14 BITS

20-BIT CLIP

IF VAL ≤ (220 – 1)

VAL = VAL

ELSE VAL = 220 – 1

14-BIT

ADC

FIFO

32-BIT DATA

REGISTERS

16-BIT

DATA

REGISTERS

0x11[13]

Figure 15. ADPD103 Datapath

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