TMS320VC5407 datasheet(32/110 Pages) TI

32 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

3.6.2 Programmable Bank-Switching

Programmable bank-switching logic allows the 5407/5404 to switch between external memory banks without

requiring external wait states for memories that need additional time to turn off. The bank-switching logic

automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or

data space.

Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at

address 0029h. The bit fields of the BSCR are shown in Figure 3−9 and are described in Table 3−5.

CONSEC

DIVFCT

IACKOFF

Reserved

R/W-1

R/W-11

R/W-1

Reserved

HBH

Reserved

R/W-0

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−9. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 3−5. Bank-Switching Control Register (BSCR) Fields

BIT

NAME

RESET

VALUE

FUNCTION

Consecutive bank-switching. Specifies the bank-switching mode.

CONSEC†

CONSEC = 0:

Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for

continuous memory reads (i.e., no starting and trailing cycles between read cycles).

CONSEC

CONSEC = 1:

Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:

CONSEC 1:

Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:

starting cycle, read cycle, and trailing cycle.

CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency

equal to 1/(DIVFCT+1) of the DSP clock.

13 14

DIVFCT

DIVFCT = 00:

CLKOUT is not divided.

13−14

DIVFCT

DIVFCT = 01:

CLKOUT is divided by 2 from the DSP clock.

DIVFCT = 10:

CLKOUT is divided by 3 from the DSP clock.

DIVFCT = 11:

CLKOUT is divided by 4 from the DSP clock (default value following reset).

IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.

IACKOFF

IACKOFF = 0: The IACK signal output off function is disabled.

IACKOFF

IACKOFF = 1: The IACK signal output off function is enabled.

11−3

Reserved

−

Reserved

HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset

HBH

HBH = 0:

The bus holder is disabled except when HPI16=1.

HBH

HBH = 1:

The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous

logic level.

Bus holder. Controls the bus holder. BH is cleared to 0 at reset.

BH = 0:

The bus holder is disabled.

BH = 1:

The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic

level.

Reserved

−

Reserved

† For additional information, see Section 3.11 of this document.

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