TMS320VC5407 datasheet(24/110 Pages) TI

24 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

3.1.2 Program Memory

Software can configure their memory cells to reside inside or outside of the program address map. When the

cells are mapped into program space, the device automatically accesses them when their addresses are

within bounds. When the program-address generation (PAGEN) logic generates an address outside its

bounds, the device automatically generates an external access. The advantages of operating from on-chip

memory are as follows:

•

Higher performance because no wait states are required

•

Lower cost than external memory

•

Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

3.1.3 Extended Program Memory

The 5407/5404 uses a paged extended memory scheme in program space to allow access of up to 8192K

of program memory. In order to implement this scheme, the 5407/5404 includes several features which are

also present on C548/549/5410:

•

Twenty-three address lines, instead of sixteen

•

An extra memory-mapped register, the XPC

•

Six extra instructions for addressing extended program space

Program memory in the 5407/5404 is organized into 128 pages that are each 64K in length.

The value of the XPC register defines the page selection. This register is memory-mapped into data space

to address 001Eh. At a hardware reset, the XPC is initialized to 0.

3.2

On-Chip ROM With Bootloader

The 5407 features a 128K-word × 16-bit on-chip maskable ROM that is mapped into program memory space,

but 16K words of which can also optionally be mapped into data memory. The 5404 features a 64K-word ×

16-bit on-chip maskable ROM that is mapped into program memory space.

Customers can also arrange to have the ROM of the 5407/5404 programmed with contents unique to any

particular application.

A bootloader is available in the standard 5407/5404 on-chip ROM. This bootloader can be used to

automatically transfer user code from an external source to anywhere in the program memory at power up.

If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the

on-chip ROM. This location contains a branch instruction to the start of the bootloader program.

The standard 5407/5404 devices provide different ways to download the code to accommodate various

system requirements:

•

Parallel from 8-bit or 16-bit-wide EPROM

•

Parallel from I/O space, 8-bit or 16-bit mode

•

Serial boot from serial ports, 8-bit or 16-bit mode

•

UART boot mode

•

Host-port interface boot

•

Warm boot

TMS320VC5407 датащи(PDF) 24 Page - Texas Instruments

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