TMS320VC5407 datasheet(13/110 Pages) TI

13 / 110 page

Features

November 2001 − Revised April 2004

SPRS007D

TMS320VC5407/TMS320VC5404 Features

D Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

D 40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

D 17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

D Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

D Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

D Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

D Data Bus With a Bus Holder Feature

D Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program

Space

D On-Chip ROM

− 128K × 16-Bit (5407) Configured for

Program Memory

− 64K × 16-Bit (5404) Configured for

Program Memory

D On-Chip RAM

− 40K x 16-Bit (5407) Composed of

Five Blocks of 8K × 16-Bit On-Chip

Dual-Access Program/Data RAM

− 16K x 16-Bit (5404) Composed of

Two Blocks of 8K × 16-Bit On-Chip

Dual-Access Program/Data RAM

D Enhanced External Parallel Interface (XIO2)

D Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

D Block-Memory-Move Instructions for Better

Program and Data Management

D Instructions With a 32-Bit Long Word

Operand

D Instructions With Two- or Three-Operand

Reads

D Arithmetic Instructions With Parallel Store

and Parallel Load

D Conditional Store Instructions

D Fast Return From Interrupt

D On-Chip Peripherals

− Software-Programmable Wait-State

Generator and Programmable

Bank-Switching

− On-Chip Programmable Phase-Locked

Loop (PLL) Clock Generator With

External Clock Source

− Two 16-Bit Timers

− Six-Channel Direct Memory Access

(DMA) Controller

− Three Multichannel Buffered Serial Ports

(McBSPs)

− 8/16-Bit Enhanced Parallel Host-Port

Interface (HPI8/16)

− Universal Asynchronous Receiver/

Transmitter (UART) With Integrated Baud

Rate Generator

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

D CLKOUT Off Control to Disable CLKOUT

D On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1† (JTAG) Boundary Scan

Logic

D 144-Pin Ball Grid Array (BGA)

(GGU Suffix)

D 144-Pin Low-Profile Quad Flatpack (LQFP)

(PGE Suffix)

D 8.33-ns Single-Cycle Fixed-Point

Instruction Execution Time (120 MIPS)

D 3.3-V I/O Supply Voltage

D 1.5-V Core Supply Voltage

† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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