TMS320VC5407 datasheet(72/110 Pages) TI

72 / 110 page

Electrical Specifications

November 2001 − Revised April 2004

SPRS007D

5.4

Package Thermal Resistance Characteristics

Table 5−1 provides the estimated thermal resistance characteristics for the recommended package types

used on the TMS320VC5407/TMS320VC5404 DSP.

Table 5−1. Thermal Resistance Characteristics

PARAMETER

GGU

PACKAGE

PGE

PACKAGE

UNIT

RΘJA

°C/W

RΘJC

°C/W

5.5

Timing Parameter Symbology

Timing parameter symbols used in the timing requirements and switching characteristics tables are created

in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related

terminology have been abbreviated as follows:

Lowercase subscripts and their meanings:

Letters and symbols and their meanings:

access time

High

cycle time (period)

Low

delay time

Valid

dis

disable time

High impedance

enable time

fall time

hold time

rise time

setup time

transition time

valid time

pulse duration (width)

Unknown, changing, or don’t care level

5.6

Internal Oscillator With External Crystal

The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent;

see Section 3.10) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock

frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by

the bit settings in the CLKMD register.

The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series

resistance of 30 Ω maximum and power dissipation of 1 mW. The connection of the required circuit, consisting

of the crystal and two load capacitors, is shown in Figure 5−2. The load capacitors, C1 and C2, should be

chosen such that the equation below is satisfied. CL (recommended value of 10 pF) in the equation is the load

specified for the crystal.

L +

C1C2

(C1 ) C2)

Table 5−2. Input Clock Frequency Characteristics

MIN

MAX

UNIT

Input clock frequency

10†

20‡

MHz

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz

‡ It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.

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