TMS320VC5407 datasheet(74/110 Pages) TI

74 / 110 page

Electrical Specifications

November 2001 − Revised April 2004

SPRS007D

Table 5−4 and Table 5−5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5−3).

Table 5−4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements

MIN

MAX

UNIT

tc(CI)

Cycle time, X2/CLKIN

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

tw(CIL)

Pulse duration, X2/CLKIN low

tw(CIH)

Pulse duration, X2/CLKIN high

Table 5−5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

8.33†

‡

td(CIH-CO)

Delay time, X2/CLKIN high to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H − 3

H + 3

tw(COH)

Pulse duration, CLKOUT high

H − 3

H + 3

† It is recommended that the PLL clocking option be used for maximum frequency operation.

‡ This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

tr(CO)

tf(CO)

CLKOUT

X2/CLKIN

tw(COL)

td(CIH-CO)

tf(CI)

tr(CI)

tc(CO)

tc(CI)

tw(COH)

tw(CIH)

tw(CIL)

NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not

divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.

Figure 5−3. External Divide-by-Two Clock Timing

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