TMS320VC5407 datasheet(96/110 Pages) TI

96 / 110 page

Electrical Specifications

November 2001 − Revised April 2004

SPRS007D

5.14.3

McBSP as SPI Master or Slave Timing

Table 5−25 to Table 5−32 assume testing over recommended operating conditions (see Figure 5−24,

Figure 5−25, Figure 5−26, and Figure 5−27).

Table 5−25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)†

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(BDRV-BCKXL)

Setup time, BDR valid before BCLKX low

2 − 6P‡

th(BCKXL-BDRV)

Hold time, BDR valid after BCLKX low

5 + 12P‡

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ P = 0.5 * processor clock

Table 5−26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†

PARAMETER

MASTER§

SLAVE

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low¶

T − 3

T + 4

td(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high#

C − 4

C + 3

td(BCKXH-BDXV)

Delay time, BCLKX high to BDX valid

− 4

5 6P + 2‡ 10P + 17‡

tdis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from

BCLKX low

C − 2

C + 3

tdis(BFXH-BDXHZ)

Disable time, BDX high impedance following last data bit from

BFSX high

2P− 4‡

6P + 17‡

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

4P+ 2‡

8P + 17‡

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ P = 0.5 * processor clock

§ T = BCLKX period = (1 + CLKGDV) * 2P

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even

¶ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

# BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

tsu(BDRV-BCLXL)

td(BCKXH-BDXV)

th(BCKXL-BDRV)

tdis(BFXH-BDXHZ)

tdis(BCKXL-BDXHZ)

th(BCKXL-BFXL)

td(BFXL-BDXV)

td(BFXL-BCKXH)

LSB

MSB

Figure 5−24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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