TMS320VC5407 datasheet(34/110 Pages) TI

34 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

When the HPI16 pin is connected to a logic “0”, the 5407/5404 HPI is configured as an HPI8. The HPI8 is an

8-bit parallel port for interprocessor communication. The features of the HPI8 include:

Standard features:

•

Sequential transfers (with autoincrement) or random-access transfers

•

Host interrupt and C54x interrupt capability

•

Multiple data strobes and control pins for interface flexibility

The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers

are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with

the HPI8 through three dedicated registers — the HPI address register (HPIA), the HPI data register (HPID),

and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the

HPIC register is accessible by both the host and the 5407/5404.

Enhanced features:

•

Access to entire on-chip RAM through DMA bus

•

Capability to continue transferring during emulation stop

The HPI16 is an enhanced 16-bit version of the TMS320C54x DSP 8-bit host-port interface (HPI8). The

HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master

of the interface. Some of the features of the HPI16 include:

•

16-bit bidirectional data bus

•

Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts

•

Only nonmultiplexed address/data modes are supported

•

18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal

extended address pages)

•

HRDY signal to hold off host accesses due to DMA latency

•

The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP.

NOTE: Only the nonmultiplexed mode is supported when the 5407/5404 HPI is configured as

a HPI16 (see Figure 3−10).

The 5407/5404 HPI functions as a slave and enables the host processor to access the on-chip memory. A

major enhancement to the 5407/5404 HPI over previous versions is that it allows host access to the entire

on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times

and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to

the same location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are

always synchronized to the 5407/5404 clock, an active input clock (CLKIN) is required for HPI accesses during

IDLE states, and host accesses are not allowed while the 5407/5404 reset pin is asserted.

TMS320VC5407 датащи(PDF) 34 Page - Texas Instruments

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