PC87365 datasheet(153/215 Pages) NSC

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9.0 Voltage Level Monitor (VLM) (Continued)

153

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Figure 28. VLM Functional Diagram

9.2.1

Voltage Measurement, Channels 0 through 10

Voltage is measured relative to (2.45

±0.05)

*VREF (where VREF is the voltage of the VREF input or the internal reference volt-

age). The results are output to the Read Channel Voltage (RDCHV) register associated with the channel. The voltage mea-

sured is:

Vi = (2.45±0.05)*VREF *RDCHVi / 256

VSB,VDD and AVDD are internally divided by two. Therefore, the readouts are half their actual values. When external dividers

are used to scale input voltage to within the dynamic range of the A/D Converter, appropriate scale factors should be taken

into account.

VHIGH and VLOW Limits, ALARM Output, IRQ and SMI

The voltage reading is compared to two limits: VHIGH and VLOW. If the voltage reading is outside any of these limits, the

respective status bit (Channel High Limit Exceeded or Channel Low Limit Exceeded) in the VCHCFST register is set. The

status bit stays active until it is cleared by the software. An ALARM status bit in the VEVSTS0 or VEVSTS1 register is set

when the Channel High Limit Exceeded or the Channel Low Limit Exceeded bit for the respective channel is set.

The ALARM output is used to indicate to the system that a voltage outside the high/low limits was detected. The ALARM

output Enable bit in the VCHCFST register enables the ALARM output to be active when the Channel High Limit Exceeded

or the Channel Low Limit Exceeded status bit in the VCHCFST register is set.

The SMI output generates an interrupt if any enabled SMI event occurs. Each bit in the VEVSTS0/1 register has a corre-

sponding SMI Enable bit in the VEVSMI0/1 register. When any status bit and its corresponding SMI Enable bit are set, the

SMI output is active.

The IRQ output generates an interrupt if any enabled IRQ event occurs. Each bit in the VEVSTS0/1 register has a corre-

sponding IRQ Enable bit in the VEVIRQ0/1 register. When any status bit and its corresponding IRQ Enable bit are set, the

IRQ output is active.

A/D

11:1

Analog

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

MUX

AVss

VLM

Analog

Power

3.3V

Converter

VIN0

AVI0

AVI6

VIN0

VIN6

AD8

VSB

VDD

AD9

VBAT

Low

High

Alarm Enable

VREF

IRQ

ALARM

SMI

AVDD

REF

Internal

VREF

*(2.45

A/D Converter

Clock

Divider

Clock

Control Logic

Status,

Data & Conﬁg

Registers

Delay

Start

VSB

Power

AD10

AVDD

and

Conﬁguration

Logic

±0.05)

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