PC87365 datasheet(85/215 Pages) NSC

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3.0 System Wake-Up Control (SWC) (Continued)

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3.4.1

SWC Register Map

The following tables list the SWC registers. For the SWC register bitmap, see Section 3.5.

Table 36. Banks 0, 1, 2 and 3 - The Common Control and Status Register Map

Table 37. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Conﬁguration and Control Register Map

Table 38. Bank 1 - CEIR Wake-Up Conﬁguration and Control Register Map

Offset

Mnemonic

Type

Section

00h

WK_STS0

Wake-Up Events Status 0

R/W1C

3.4.2

01h

WK_STS1

Wake-Up Events Status 1

R/W1C

3.4.3

02h

WK_EN0

Wake-Up Enable 0

R/W

3.4.4

03h

WK_EN1

Wake-Up Enable 1

R/W

3.4.5

04h

WK_CFG

Wake-Up Conﬁguration

R/W

3.4.6

05h-07h

Reserved

08h

SB_GPDO0

Standby GPIOE/GPIE Data Out 0

R/W

3.4.33

09h

SB_GPDI0

Standby GPIOE/GPIE Data In 0

3.4.34

0Ah

SB_GPDO1

Standby GPOS Data Out 1

R/W

3.4.35

0Bh

SB_GPDI1

Standby GPIS Data In 1

3.4.36

0Ch-12h

Reserved

Offset

Mnemonic

Type

Section

13h

PS2CTL

PS/2 Protocol Control

R/W

3.4.18

14h-15h

Reserved

16h

KDSR

Keyboard Data Shift

3.4.19

17h

MDSR

Mouse Data Shift

3.4.20

18h-1Fh

PS2KEY0-PS2KEY7 PS/2 Keyboard Key Data

R/W

3.4.21

Offset

Mnemonic

Type

Section

13h

IRWCR

CEIR Wake-Up Control

R/W

3.4.22

14h

Reserved

15h

IRWAD

CEIR Wake-Up Address

R/W

3.4.23

16h

IRWAM

CEIR Wake-Up Address Mask

R/W

3.4.24

17h

ADSR

CEIR Address Shift

R/O

3.4.25

18h

IRWTR0L

CEIR Wake-Up, Range 0, Low Limit

R/W

3.4.26

19h

IRWTR0H

CEIR Wake-Up, Range 0, High Limit

R/W

3.4.26

1Ah

IRWTR1L

CEIR Wake-Up, Range 1, Low Limit

R/W

3.4.27

1Bh

IRWTR1H

CEIR Wake-Up, Range 1, High Limit

R/W

3.4.27

1Ch

IRWTR2L

CEIR Wake-Up, Range 2, Low Limit

R/W

3.4.28

1Dh

IRWTR2H

CEIR Wake-Up, Range 2, High Limit

R/W

3.4.28

1Eh

IRWTR3L

CEIR Wake-Up, Range 3, Low Limit

R/W

3.4.29

1Fh

IRWTR3H

CEIR Wake-Up, Range 3, High Limit

R/W

3.4.29

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