| поискавой системы для электроныых деталей |
|
PC87365 датащи(PDF) 56 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87365 датащи(HTML) 56 Page - National Semiconductor (TI) |
|
56 / 215 page ![]() 2.0 Device Architecture and Configuration (Continued) 56 www.national.com 2.10 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION 2.10.1 General Description The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible. The PC87365 FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including: q FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/read- ing from a diskette, where: 0 = FM mode 1 = MFM mode q A logic 1 is returned for all floating (TRI-STATE) FDC register bits upon LPC I/O read cycles. Exceptions to standard FDC support include: q Automatic media sense is not supported (MSEN0-1 pins are not implemented) q DRATE1 is not supported. Table 17 lists the FDC functional block registers. Table 17. FDC Registers 2.10.2 Logical Device 0 (FDC) Configuration Table 18 lists the Configuration registers that affect the FDC. Only the last two registers (F0h and F1h) are described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others. Table 18. FDC Configuration Registers Offset1 1. This is the 8-byte aligned FDC base address. Mnemonic Register Name Type 00h SRA Status A RO 01h SRB Status B RO 02h DOR Digital Output R/W 03h TDR Tape Drive R/W 04h MSR Main Status R DSR Data Rate Select W 05h FIFO Data (FIFO) R/W 06h N/A X 07h DIR Digital Input R CCR Configuration Control W Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register and bit 0 of the SIOCF6 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 03h 61h Base Address LSB register bits 2 and 0 (for A2 and A0) are read only, 00b. R/W F2h 70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 06h 71h Interrupt Type. Bit 1 is read/write; other bits are read only. R/W 03h 74h DMA Channel Select. R/W 02h 75h Report no second DMA assignment. RO 04h F0h FDC Configuration register. R/W 24h F1h Drive ID register. R/W 00h |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |