PC87365 datasheet(61/215 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.11.3

Parallel Port Configuration Register

This register is reset by hardware to F2h.

Location:

Index F0h

Type:

R/W

Bit

76543210

Name

Parallel Port Mode Select

Extended

Access

Reserved

Power

Mode

Control

TRI-STATE

Control

Reset

11110010

Bit

Description

7-5

Parallel Port Mode Select.

Bits

7 6 5

Function

0 0 0

SPP-Compatible mode

PD7-0 are always output signals

0 0 1

SPP Extended mode

PD7-0 direction is controlled by software

0 1 0

EPP 1.7 mode

0 1 1

EPP 1.9 mode

1 0 0

ECP mode (IEEE1284 register set), with no support for EPP mode

1 0 1

Reserved

1 1 0

Reserved

1 1 1

ECP mode (IEEE1284 register set), with EPP mode selectable as Mode 4

Selection of EPP 1.7 or 1.9 in ECP Mode 4 is controlled by bit 4 of the Control2 configuration register of

the parallel port at offset 02h.

Note: Before setting bits 7-5, enable the parallel port and set CTR/DCR (at base address + 2) to C4h.

Extended Register Access.

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).

1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-

time conﬁguration within the Parallel Port address space.

3-2

Reserved.

Power Mode Control. When the logical device is active:

0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is

active. Registers are maintained.

1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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