PC87365 datasheet(38/215 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.2.6

Power States

The following terminology is used in this document to describe the various possible power states:

• Power On

Both VSB and VDD are active.

• Power Off

VSB is active and VDD is inactive.

• Power Fail

Both VSB and VDD are inactive.

Note:

The following state is illegal: VDD active and VSB inactive.

2.2.7

Address Decoding

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional

blocks. However, the number of configurable bits in the base address registers varies for each logical device.

The lower 1, 2, 3, 4 or 5 address bits are decoded within the functional block to determine the offset of the accessed register

within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base

address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address

register are forced to 0 (read only) and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size

of the I/O range.

The base address of the FDC, Serial Port 1, Serial Port 2 with IR and KBC are limited to the I/O address range of 00h to

7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h.

The addresses of the non-legacy logical devices are configurable within the full 16-bit address range (up to FFFXh).

In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel

Port). The KBC has two I/O descriptors with some implied dependency between them. For more details, see the description

of the base address register for each logical device.

2.3

INTERRUPT SERIALIZER

The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from external devices, via the PIRQn

pins, into serial interrupt request data transmitted over the SERIRQ bus. This enables the integration of devices that support

only parallel IRQ in a system which supports only serial IRQs. Figure 4 shows the interrupt serialization mechanism.

Figure 4. Interrupt Serialization Mechanism

PIRQ signals that enter the device are fed into an IRQ sharing mechanism. This mechanism combines them with internal

IRQ signals that are mapped to their associated IRQ slots. The resulting internal shared IRQs are then fed into the Interrupt

Serializer, where they are translated into serial data and transmitted over the SERIRQ bus.

The IRQ sharing mechanism allows an internal IRQ and an external PIRQ to share the same IRQ slot. To share an IRQ slot,

all IRQ sources routed to it, including possibly a PIRQn pin, must be active low. When multiple IRQ sources are set to share

an IRQ slot, the corresponding internal IRQ signal is a logic AND of all IRQ sources.

When an IRQ slot is exclusively used by a PIRQ pin, each transition sensed on this PIRQ pin is translated into a new value.

This value is transmitted over the SERIRQ bus during the corresponding IRQ slot. A transition on PIRQn results in a new

value that is transmitted during IRQ slot “n” of the SERIRQ bus. For example, a transition on PIRQ3 is translated into the

IRQ Mapping

and Polarity

Control

IRQ Sharing

Mechanism

Internal

IRQ

Sources

Internal

Polarity/

Control

Signals

PIRQn Pins

Shared PIRQs

IRQ3

IRQ15

Interrupt

Serializer

Mapped

IRQs

Non-Shared

Bus Interface

SERIRQ

Mapping

PIRQs

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