PC87365 datasheet(31/215 Pages) NSC

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2.0

Device Architecture and Conﬁguration

The PC87365 SuperI/O device comprises a collection of generic and proprietary functional blocks. Each functional block is

described in a separate chapter in this document. However, some parameters in the implementation of each functional block

may vary per SuperI/O device. This chapter describes the PC87365 structure and provides all logical device specific infor-

mation, including special implementation of generic blocks, system interface and device configuration.

2.1

OVERVIEW

The PC87365 consists of 13 logical devices, the host interface and a central set of configuration registers, all built around a

central internal bus. The internal bus is similar to an 8-bit ISA bus protocol. See Figure 1, which illustrates the blocks and

related logic.

The system interface serves as a bridge between the external LPC Interface and the internal bus. It supports 8-bit I/O Read,

8-bit I/O Write and 8-bit DMA transactions, as defined in Intel’s

LPC Interface Speciﬁcation, Revision 1.0.

The central configuration register set supports ACPI-compliant PnP configuration. The configuration registers are structured as

a subset of the Plug and Play Standard registers, defined in Appendix A of the

Plug and Play ISA Specification, Revision 1.0a

by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels and IRQ lines)

are configured in, and managed by, the central configuration register set. In addition, some function-specific parameters are

configurable through the configuration registers and distributed to the functional blocks through special control signals.

2.2

CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is comprised of a set of banked registers that are accessed via a pair of specialized registers.

2.2.1

The Index-Data Register Pair

Access to the SuperI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations.

The base address of this register pair is determined during reset, according to the state of the hardware strapping option on

the BADDR pin. Table 5 shows the selected base addresses as a function of BADDR.

Table 5. BADDR Strapping Options

The Index register is an 8-bit R/W register located at the selected base address (Base+0). It is used as a pointer to the con-

figuration register file and holds the index of the configuration register that is currently accessible via the Data register. Read-

ing the Index register returns the last value written to it (or the default of 00h after reset).

The Data register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the Data register

actually accesses the configuration register that is currently pointed to by the Index register.

BADDR

I/O Address

Index Register

Data Register

2Eh

2Fh

4Eh

4Fh

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