PC87365 datasheet(78/215 Pages) NSC

78 / 215 page

2.0 Device Architecture and Configuration (Continued)

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2.19 WATCHDOG TIMER (WDT) CONFIGURATION

2.19.1

Logical Device 10 (WDT) Configuration

Table 33 lists the configuration registers that affect the WATCHDOG Timer. Only the last register (F0h) is described here.

See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 33. WDT Conﬁguration Registers

2.19.2

WATCHDOG Timer Configuration Register

This register is reset by hardware to 02h.

Location:

Index F0h

Type:

R/W

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h

Base Address MSB register.

R/W

00h

61h

Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b.

R/W

00h

70h

Interrupt Number (for routing the WDO signal) and Wake-Up on IRQ Enable

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment.

04h

75h

Report no DMA assignment.

04h

F0h

WATCHDOG Timer Conﬁguration register.

R/W

02h

Bit

76543210

Name

Reserved

Output

Type

Internal

Pull-Up

Enable

Power

Mode

Control

TRI-STATE

Control

Reset

00000010

Bit

Description

7-4

Reserved.

Output Type. This bit controls the buffer type (open-drain or push-pull) of the WDO pin.

0: Open-drain (default)

1: Push-pull

Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the WDO pin.

0: Disabled (default)

1: Enabled

Power Mode Control.

0: Low power mode:

WATCHDOG Timer clock disabled. WDO output signal is set to 1. Registers are accessible and maintained

(unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers).

1: Normal power mode:

WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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