CS8952T datasheet(43/86 Pages) CIRRUS

43 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

Interrupt Mask Register - Address 10h (Cont.)

BIT

NAME

TYPE

RESET

DESCRIPTION

Auto-Neg Complete Read/Write 0

When set, an interrupt will be generated once auto-

negotiation has completed successfully.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Parallel Detection

Fault

Read/Write 0

When set, an interrupt will be generated if auto-nego-

tiation determines that unstable legacy link signaling

was received.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Parallel Fail

Read/Write 0

When set, an interrupt will be generated when paral-

lel detection has occurred for a technology that is not

currently advertised by the local device.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Remote Fault

Read/Write 0

When set, an interrupt will be generated if a remote

fault condition is detected either by auto-negotiation

or by the Far-End Fault Detect state machine.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Page Received

Read/Write 0

When set, an interrupt is generated each time a page

is received during auto-negotiation.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Reserved

Read Only

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