CS8952T datasheet(24/86 Pages) CIRRUS

24 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

Reset Operation

Reset occurs in response to six different conditions:

1) There is a chip-wide reset whenever the RE-

SET pin is high for at least 200 ns. During a

chip-wide reset, all circuitry and registers in the

CS8952T are reset.

2) When power is applied, the CS8952T main-

tains reset until the voltage at the VDD supply

pins

reaches

approximately

3.6 V.

The

CS8952T comes out of reset once VDD is

greater than approximately 3.6 V and the crys-

tal oscillator has stabilized.

3) There is a chip-wide reset whenever the RE-

SET bit (bit 15 of the Basic Mode Control Reg-

ister (address 00h)) is set.

4) Digital circuitry is reset whenever bit 0 of the

PCS Sub-Layer Configuration Register (ad-

dress 17h) is set. Analog circuitry is unaffected.

5) Analog circuitry is reset and recalibrated when-

ever the CS8952T enters or exits the power-

down state, as requested by pin PWRDN.

6) Analog circuitry is reset and recalibrated when-

ever the CS8952T changes between 10 Mb/s

and 100 Mb/s modes.

After a reset, the CS8952T latches the signals on

various input pins in order to initialize key registers

and goes through a self configuration. This in-

cludes calibrating on-chip analog circuitry. Time

required for the reset calibration is typically 40 ms.

External circuitry may access registers internal to

the CS8952T during this time. Reset and calibra-

tion complete is indicated when bit 15 of the Basic

Mode Control Register (address 00h) is clear.

LED Indicators

The LEDx, SPD100, and SPD10 output pins pro-

vide status information that can be used to drive

LEDs or can be used as inputs to external control

circuitry. Indication options include: receive activ-

ity, transmit activity, collision, carrier sense, polar-

ity OK, descrambler synchronization status, auto-

negotiation status, speed (10 vs. 100), and duplex

mode.

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