CS8952T datasheet(25/86 Pages) CIRRUS

25 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

MEDIA INDEPENDENT INTERFACE

The Media Independent Interface (MII) provides a

simple interconnect to an external Media Access

Controller (MAC). This connection may be chip to

chip, motherboard to daughterboard, or a connec-

tion between two assemblies attached by a limited

length of shielded cable and an appropriate connec-

tor.

The CS8952T's MII interface is enhanced beyond

IEEE requirements by register extensions and the

addition of pins for MII_IRQ,RX_EN,and ISO-

DEF signals. The MII_IRQ pin provides an inter-

rupt signal to the controller when a change of state

has occurred in the CS8952T, eliminating the need

for the system to poll the CS8952T for state chang-

es. The RX_EN signal allows the receiver outputs

to be electrically isolated. The ISODEF pin con-

trols the value of register bit ISOLATE in the Basic

Mode Control Register (address 00h) which in turn

electrically isolates the CS8952T's MII data path.

The MII interface uses the following pins:

STATUS Pins

COL - Collision indication, valid only for

half duplex modes.

CRS - Carrier Sense indication

SERIAL MANAGEMENT Pins

MDIO - a bi-directional serial data path

MDC - clock for MDIO (16.7 MHz max)

MII_IRQ - Interrupt indicating change in

the Interrupt Status Register (address 11h)

RECEIVE DATA Pins

RXD[3:0] - Parallel data output path

RX_CLK - Recovered clock output

RX_DV - Indicates when receive data is

present and valid

RX_ER - Indicates presence of error in re-

ceived data

RX_EN - Can be used to tri-state receiver

output pins

TRANSMIT DATA Pins

TXD[3:0] - Parallel data input path

TX_CLK - Transmit clock

TX_EN - Indicates when transmit data is

present and valid

TX_ER - Request to transmit a 100BASE-

T HALT symbol, ignored for 10BASE-T

operation.

The interface uses TTL signal levels, which are

compatible with devices operating at a nominal

supply voltage of either 5.0 or 3.3 volts. It is capa-

ble of supporting either 10 Mb/s or 100 Mb/s data

rates transparently. That is, all signaling remains

identical at either data rate; only the nominal clock

frequency is changed.

MII Frame Structure

Data frames transmitted through the MII have the

following format:

Each frame is preceded by an inter-frame gap. The

inter-frame gap is an unspecified time during

whichnodataactivityoccursonthe mediaasindi-

cated by the de-assertion of CRS for the receive

path and TX_EN for the transmit path.

The Preamble consists of seven bytes of 10101010.

The Start of Frame Delimiter consists of a single

byte of 10101011.

Data may be any number of bytes.

The End of Frame Delimiter is conveyed by the de-

assertion of RX_DV and TX_EN for receive and

transmit paths, respectively.

Preamble

(7 Bytes)

Start of

Frame

Delimiter

(1 Byte)

Data

End of

Frame

Delimiter

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