CS8952T datasheet(22/86 Pages) CIRRUS

22 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

Section 14.2.1.1 of the Ethernet standard. Trans-

mitted link pulses are positive pulses, one bit time

wide, typically generated at a rate of one every

16 ms. The 16 ms timer also starts whenever the

transmitter completes an End-of-Frame (EOF) se-

quence. Thus, a link pulse will be generated 16 ms

after an EOF unless there is another transmitted

packet.

Link Polarity Detection

The CS8952T automatically checks the polarity of

the receive half of the twisted pair cable. To detect

a reversed pair, the receiver examines received link

pulses and the End-of-Frame (EOF) sequence of

incoming packets. If it detects at least one reversed

link pulse and at least four frames in a row with

negative polarity after the EOF, the receive pair is

considered reversed.

If the polarity is reversed and the Polarity Disable

bit of the 10BASE-T Configuration Register (ad-

dress 1Ch) is clear, the CS8952T automatically

corrects a reversal.

SQE (Heartbeat) Test Function

When SQE is enabled, the CS8952T will assert the

COL pin for approximately 10 bit times within 1

µs

after the transmission of each packet.

The SQE function is disabled by default when the

REPEATER pin is deasserted on reset or power-

up. It may be enabled through the SQE Enable bit

in the 10BASE-T Configuration Register (address

1Ch).

Receiver Squelch

The 10BASE-T squelch circuit determines when

valid data is present on the RXD+/RXD- pair. In-

coming signals passing through the receive filter

are tested by the squelch circuit. Any signal with

amplitude less than the squelch threshold (either

positive or negative, depending on polarity) is re-

jected.

10BASE-T Loopback

When Loopback is selected, the TXD[3:0] pins are

looped back into the RXD[3:0] pins through the

Manchester Encoder and Decoder. Selection is

made via:

setting bit 14 in the Basic Mode Control

setting bits 8 and 11 in the Loopback, By-

pass, and Receiver Error Mask Register

(address 18h) or

asserting the LPBK pin.

10BASE-T Serial Application

This mode is selected when pin 10BT_SER is as-

serted during power-up or reset, and operates simi-

lar to the 10BASE_T MII mode except that data is

transferred serially on pins RXD0 and TXD0 using

a 10 MHz RX_CLK and TX_CLK. Receive data is

framed by CRS rather than RX_DV.

Auto-Negotiation

The CS8952T supports auto-negotiation, which is

the mechanism that allows the two devices on ei-

ther end of an Ethernet link segment to share infor-

mation and automatically configure both devices

for maximum performance. When configured for

auto-negotiation, the CS8952T will detect and au-

tomatically operate full-duplex at 100 Mb/s if the

device on the other end of the link segment also

supports full-duplex, 100 Mb/s operation, and

auto-negotiation. The CS8952T auto-negotiation

capability is fully compliant with the relevant por-

tions of section 28 of the IEEE 802.3u standard.

The CS8952T can auto-negotiate both operating

speed (10 versus 100 Mb/s), duplex mode (half du-

plex versus full duplex), and flow control (pause

frames), or alternatively can be set not to negotiate.

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