TMS570LS0332PZ datasheet(90/110 Pages) TI1

90 / 110 page

TMS570LS0432, TMS570LS0332

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

www.ti.com

7.7.5

SPI Slave Mode I/O Timings

Table 7-15. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =

input, and SPISOMI = output)(1)(2)(3)(4)

NO.

PARAMETER

MIN

MAX

UNIT

tc(SPC)S

Cycle time, SPICLK(5)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

2(6)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

3(6)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

td(SPCH-SOMI)S

Delay time, SPISOMI valid after SPICLK high (clock polarity = 0)

trf(SOMI) + 20

4(6)

td(SPCL-SOMI)S

Delay time, SPISOMI valid after SPICLK low (clock polarity = 1)

trf(SOMI) + 20

Hold time, SPISOMI data valid after SPICLK high (clock polarity

th(SPCH-SOMI)S

=0)

5(6)

Hold time, SPISOMI data valid after SPICLK low (clock polarity

th(SPCL-SOMI)S

=1)

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity = 0)

6(6)

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock polarity = 1)

Hold time, SPISIMO data valid after SPICLK low (clock polarity

th(SPCL-SIMO)S

= 0)

7(6)

Hold time, SPISIMO data valid after S PICLK high (clock polarity

th(SPCH-SIMO)S

= 1)

Delay time, SPIENAn high after last SPICLK low (clock polarity

2.5tc(VCLK)+tr(ENA

td(SPCL-SENAH)S

1.5tc(VCLK)

= 0)

n)+ 22

Delay time, SPIENAn high after last SPICLK high (clock polarity

2.5tc(VCLK)+

td(SPCH-SENAH)S

1.5tc(VCLK)

= 1)

tr(ENAn) + 22

Delay time, SPIENAn low after SPICSn low (if new data has

tc(VCLK)+tf(ENAn)+

td(SCSL-SENAL)S

tf(ENAn)

been written to the SPI buffer)

(1)

The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2)

If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3)

For rise and fall timings, see Table 5-6.

(4)

tc(VCLK) = interface clock cycle time = 1 /f(VCLK)

(5)

When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.

(6)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Peripheral Information and Electrical Specifications

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