TMS570LS0332PZ datasheet(55/110 Pages) TI1

55 / 110 page

TMS570LS0432, TMS570LS0332

www.ti.com

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

6.14.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware

Initialization mechanism in the System module. This hardware mechanism allows an application to

program the memory arrays with error detection capability to a known state based on their error detection

scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects

the memories that are to be initialized.

For more information on these registers refer to the device Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in

Table 6-23.

Table 6-23. Memory Initialization

ADDRESS RANGE

MSINENA REGISTER

CONNECTING MODULE

BIT NO.(1)

BASE ADDRESS

ENDING ADDRESS

RAM

0x08000000

0x08007FFF

MIBSPI1 RAM

0xFF0E0000

0xFF0FFFFF

7(2)

DCAN2 RAM

0xFF1C0000

0xFF1DFFFF

DCAN1 RAM

0xFF1E0000

0xFF1FFFFF

MIBADC RAM

0xFF3E0000

0xFF3FFFFF

N2HET RAM

0xFF460000

0xFF47FFFF

HTU RAM

0xFF4E0000

0xFF4FFFFF

VIM RAM

0xFFF82000

0xFFF82FFF

(1)

Unassigned register bits are reserved.

(2)

The MibSPI1 module performs an initialization of the transmit and receive RAMs as soon as the module is brought out of reset using the

SPI Global Control Register 0 (SPIGCR0). This is independent of whether the application chooses to initialize the MibSPI1 RAMs using

the system module auto-initialization method.

System Information and Electrical Specifications

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