TMS570LS0332PZ datasheet(20/110 Pages) TI1

номер детали	TMS570LS0332PZ

подробное описание детали	16- and 32-Bit RISC Flash Microcontroller

PDF	110 Pages

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производитель	TI1 [Texas Instruments]

домашняя страница	http://www.ti.com

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20 / 110 page

ASWSTEN

Flash Address Wait States

EEPROM Emulation Memory Wait States (Bank 7)

0MHz

80MHz

EWAIT

Main Memory Data Wait States (Bank 0)

RWAIT

0MHz

80MHz

45MHz

0MHz

80MHz

67MHz

50MHz

TMS570LS0432, TMS570LS0332

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

www.ti.com

5.6

Wait States Required

The TCM RAM can support program and data fetches at full CPU speed without any address or data wait states

required. There are no registers which need to be programmed for RAM wait states.

The TCM flash can support zero address and data wait states up to a CPU speed of 45 MHz in nonpipelined

mode.The flash supports a maximum CPU clock speed of 80 MHz in pipelined mode with no address wait states

and one data wait state.

The proper wait states should be set in the register fields Address Setup Wait State Enable (ASWSTEN

0xFFF87000[4]), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT

0xFFF872B8[19:16]) as shown in Figure 5-1.

Figure 5-1. Wait States Scheme

The flash wrapper defaults to nonpipelined mode with address wait states disabled, ASWSTEN=0; the main

memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.

Specifications

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TMS570LS0332PZ датащи(PDF) 20 Page - Texas Instruments