TMS570LS0332PZ datasheet(33/110 Pages) TI1

33 / 110 page

TMS570LS0432, TMS570LS0332

www.ti.com

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

6.4.6.1

Application Sequence for CPU Self-Test

1. Configure clock domain frequencies.

2. Select the number of test intervals to be run.

3. Configure the timeout period for the self-test run.

4. Save the CPU state if required

5. Enable self-test.

6. Wait for CPU reset.

7. In the reset handler, read CPU self-test status to identify any failures.

8. Retrieve CPU state if required.

For more information, see the TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller Technical

Reference Manual (SPNU517).

6.4.6.2

CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 45 MHz. The STCCLK is divided down from the CPU clock,

when necessary. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

6.4.6.3

CPU Self-Test Coverage

Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test

cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 6-7. CPU Self-Test Coverage

INTERVALS

TEST COVERAGE, %

TEST CYCLES

60.06

1365

68.71

2730

73.35

4095

76.57

5460

78.7

6825

80.4

8190

81.76

9555

82.94

10920

83.84

12285

84.58

13650

85.31

15015

85.9

16380

86.59

17745

87.17

19110

87.67

20475

88.11

21840

88.53

23205

88.93

24570

89.26

25935

89.56

27300

89.86

28665

90.1

30030

90.36

31395

90.62

32760

System Information and Electrical Specifications

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