TMS570LS0332PZ datasheet(29/110 Pages) TI1

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3.3 V

CCIOPORH

1.2 V

CCPORH

CCIOPORL

(1.2 V)

/ V

(3.3 V)

CCIO

CCP

nPORRST

CCPORL

IL(PORRST)

/ V

CCIO

CCP

CCPORL

IL(PORRST)

CCIOPORH

CCPORH

CCIOPORL

NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.

TMS570LS0432, TMS570LS0332

www.ti.com

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

6.2.2

Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.2.3

Power-On Reset: nPORRST

This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the

recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.2.3.1

nPORRST Electrical and Timing Requirements

Table 6-4. Electrical Requirements for nPORRST

NO.

PARAMETER

MIN

MAX

UNIT

VCC low supply level when nPORRST must be active during power

VCCPORL

0.5

VCC high supply level when nPORRST must remain active during

VCCPORH

1.14

power up and become active during power down

VCCIO / VCCP low supply level when nPORRST must be active

VCCIOPORL

1.1

during power up

VCCIO / VCCP high supply level when nPORRST must remain active

VCCIOPORH

3.0

during power up and become active during power down

VIL(PORRST)

Low-level input voltage of nPORRST VCCIO > 2.5 V

0.2 * VCCIO

Low-level input voltage of nPORRST VCCIO < 2.5 V

0.5

Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL

tsu(PORRST)

during power up

th(PORRST)

Hold time, nPORRST active after VCC > VCCPORH

Setup time, nPORRST active before VCC < VCCPORH during power

tsu(PORRST)

µs

down

th(PORRST)

Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH

th(PORRST)

Hold time, nPORRST active after VCC < VCCPORL

Filter time nPORRST pin;

tf(nPORRST)

Pulses less than MIN will be filtered out, pulses greater than MAX

475

2000

will generate a reset.

Figure 6-1. nPORRST Timing Diagram

System Information and Electrical Specifications

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