TMS570LS0332PZ datasheet(37/110 Pages) TI1

37 / 110 page

/NR

/1 to /64

OSCIN

PLL

INTCLK

/OD

/1 to /8

VCOCLK

/1 to /32

post_ODCLK

/NF

/1 to /256

PLLCLK

fPLLCLK = (fOSCIN / NR) * NF / (OD * R)

TMS570LS0432, TMS570LS0332

www.ti.com

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

Figure 6-5 shows a block diagram of the internal reference oscillator. This is an LPO and provides two

clock sources: one nominally 80 kHz and one nominally 10 MHz.

6.5.1.2.2 LPO Electrical and Timing Specifications

Table 6-10. LPO Specifications

PARAMETER

MIN

TYP

MAX

UNIT

Oscillator fail frequency - lower threshold, using

1.375

2.4

4.875

untrimmed LPO output

Clock Detection

MHz

Oscillator fail frequency - higher threshold, using

38.4

untrimmed LPO output

Untrimmed frequency

5.5

19.5

MHz

Trimmed frequency

9.6

MHz

LPO - HF oscillator

Start-up time from STANDBY (LPO BIAS_EN High for

(fHFLPO)

µs

at least 900 µs)

Cold start-up time

900

µs

Untrimmed frequency

180

kHz

LPO - LF oscillator

Start-up time from STANDBY (LPO BIAS_EN High for

100

µs

(fLFLPO)

at least 900 µs)

Cold start-up time

2000

µs

6.5.1.3

Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

•

Frequency modulation can be optionally superimposed on the synthesized frequency of PLL.

•

Configurable frequency multipliers and dividers.

•

Built-in PLL Slip monitoring circuit.

•

Option to reset the device on a PLL slip detection.

6.5.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.

Figure 6-6. PLL Block Diagram

6.5.1.3.2 PLL Timing Specifications

Table 6-11. PLL Timing Specifications

PARAMETER

MIN

MAX

UNIT

fINTCLK

PLL1 Reference Clock frequency

MHz

fpost_ODCLK

Post-ODCLK – PLL1 Post-divider input clock frequency

400

MHz

fVCOCLK

VCOCLK – PLL1 Output Divider (OD) input clock frequency

150

550

MHz

System Information and Electrical Specifications

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