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TMS570LS0332PZ датащи(PDF) 74 Page - Texas Instruments |
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TMS570LS0332PZ датащи(HTML) 74 Page - Texas Instruments |
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74 / 110 page ![]() TMS570LS0432, TMS570LS0332 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 www.ti.com Table 7-7. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions PARAMETER DESCRIPTION/CONDITIONS MIN TYP MAX UNIT Conversion range over which CR specified ADREFHI - ADREFLO 3 3.6 V accuracy is maintained With ADC 1 Calibration 10-bit mode Without ADC 2 Difference between the first ideal Calibration ZSET Offset Error transition (from code 000h to 001h) and LSB(1) With ADC the actual transition 2 Calibration 12-bit mode Without ADC 4 Calibration Difference between the last ideal 10-bit mode 2 FSET Gain Error transition (from code FFEh to FFFh) LSB 12-bit mode 3 and the actual transition minus offset. Difference between the actual step 10-bit mode ± 1.5 Differential EDNL width and the ideal value. LSB nonlinearity error 12-bit mode ± 2 (See Figure 7-2) Maximum deviation from the best 10-bit mode ± 2 straight line through the MibADC. Integral EINL MibADC transfer characteristics, LSB nonlinearity error 12-bit mode ± 2 excluding the quantization error. (See Figure 7-3) With ADC ± 2 Calibration 10-bit mode Without ADC ± 4 Maximum value of the difference Calibration Total unadjusted ETOT between an analog value and the ideal LSB error With ADC midstep value. (See Figure 7-4) ± 4 Calibration 12-bit mode Without ADC ± 7 Calibration (1) 1 LSB = (ADREFHI – ADREFLO)/ 2 n where n = 10 in 10-bit mode and 12 in 12-bit mode 74 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332 |
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